Bill Wendling c844be2422 Merging r195591: ...

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r195591 | haoliu | 2013-11-24 17:53:26 -0800 (Sun, 24 Nov 2013) | 5 lines

Fixed a bug about disassembling AArch64 post-index load/store single element instructions.
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
    echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195619 91177308-0d34-0410-b5e6-96231b3b80d8

2013-11-25 06:23:37 +00:00

..

AArch64

Merging r195591:

2013-11-25 06:23:37 +00:00

ARM

[ARM] Add support for MVFR2 which is new in ARMv8

2013-11-11 19:56:13 +00:00

Mips

Support for microMIPS trap instruction with immediate operands.

2013-11-13 13:15:03 +00:00

SystemZ

[SystemZ] Add the general form of BCR

2013-11-13 16:57:53 +00:00

X86

Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.

2013-10-14 01:42:32 +00:00

XCore

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00