mirror of
https://github.com/c64scene-ar/llvm-6502.git
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3116dce338
expand the testing of the narrowing shift right instructions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
921 lines
29 KiB
C++
921 lines
29 KiB
C++
//===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of each
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// instruction in a format that the enhanced disassembler can use to tokenize
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// and parse instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "EDEmitter.h"
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#include "AsmWriterInst.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "llvm/MC/EDInstInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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#include <map>
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#include <string>
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#include <vector>
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using namespace llvm;
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///////////////////////////////////////////////////////////
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// Support classes for emitting nested C data structures //
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///////////////////////////////////////////////////////////
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namespace {
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class EnumEmitter {
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private:
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std::string Name;
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std::vector<std::string> Entries;
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public:
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EnumEmitter(const char *N) : Name(N) {
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}
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int addEntry(const char *e) {
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Entries.push_back(std::string(e));
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return Entries.size() - 1;
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}
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void emit(raw_ostream &o, unsigned int &i) {
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o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
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i += 2;
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unsigned int index = 0;
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unsigned int numEntries = Entries.size();
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for (index = 0; index < numEntries; ++index) {
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o.indent(i) << Entries[index];
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if (index < (numEntries - 1))
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o << ",";
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o << "\n";
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}
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i -= 2;
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o.indent(i) << "};" << "\n";
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}
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void emitAsFlags(raw_ostream &o, unsigned int &i) {
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o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
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i += 2;
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unsigned int index = 0;
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unsigned int numEntries = Entries.size();
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unsigned int flag = 1;
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for (index = 0; index < numEntries; ++index) {
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o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
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if (index < (numEntries - 1))
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o << ",";
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o << "\n";
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flag <<= 1;
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}
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i -= 2;
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o.indent(i) << "};" << "\n";
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}
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};
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class ConstantEmitter {
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public:
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virtual ~ConstantEmitter() { }
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virtual void emit(raw_ostream &o, unsigned int &i) = 0;
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};
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class LiteralConstantEmitter : public ConstantEmitter {
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private:
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bool IsNumber;
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union {
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int Number;
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const char* String;
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};
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public:
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LiteralConstantEmitter(int number = 0) :
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IsNumber(true),
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Number(number) {
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}
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void set(const char *string) {
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IsNumber = false;
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Number = 0;
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String = string;
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}
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bool is(const char *string) {
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return !strcmp(String, string);
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}
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void emit(raw_ostream &o, unsigned int &i) {
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if (IsNumber)
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o << Number;
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else
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o << String;
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}
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};
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class CompoundConstantEmitter : public ConstantEmitter {
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private:
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unsigned int Padding;
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std::vector<ConstantEmitter *> Entries;
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public:
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CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
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}
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CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
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Entries.push_back(e);
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return *this;
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}
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~CompoundConstantEmitter() {
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while (Entries.size()) {
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ConstantEmitter *entry = Entries.back();
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Entries.pop_back();
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delete entry;
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}
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}
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void emit(raw_ostream &o, unsigned int &i) {
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o << "{" << "\n";
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i += 2;
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unsigned int index;
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unsigned int numEntries = Entries.size();
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unsigned int numToPrint;
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if (Padding) {
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if (numEntries > Padding) {
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fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
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llvm_unreachable("More entries than padding");
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}
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numToPrint = Padding;
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} else {
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numToPrint = numEntries;
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}
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for (index = 0; index < numToPrint; ++index) {
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o.indent(i);
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if (index < numEntries)
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Entries[index]->emit(o, i);
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else
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o << "-1";
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if (index < (numToPrint - 1))
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o << ",";
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o << "\n";
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}
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i -= 2;
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o.indent(i) << "}";
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}
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};
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class FlagsConstantEmitter : public ConstantEmitter {
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private:
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std::vector<std::string> Flags;
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public:
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FlagsConstantEmitter() {
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}
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FlagsConstantEmitter &addEntry(const char *f) {
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Flags.push_back(std::string(f));
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return *this;
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}
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void emit(raw_ostream &o, unsigned int &i) {
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unsigned int index;
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unsigned int numFlags = Flags.size();
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if (numFlags == 0)
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o << "0";
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for (index = 0; index < numFlags; ++index) {
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o << Flags[index].c_str();
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if (index < (numFlags - 1))
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o << " | ";
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}
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}
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};
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}
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EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
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}
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/// populateOperandOrder - Accepts a CodeGenInstruction and generates its
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/// AsmWriterInst for the desired assembly syntax, giving an ordered list of
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/// operands in the order they appear in the printed instruction. Then, for
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/// each entry in that list, determines the index of the same operand in the
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/// CodeGenInstruction, and emits the resulting mapping into an array, filling
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/// in unused slots with -1.
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///
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/// @arg operandOrder - The array that will be populated with the operand
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/// mapping. Each entry will contain -1 (invalid index
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/// into the operands present in the AsmString) or a number
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/// representing an index in the operand descriptor array.
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/// @arg inst - The instruction to use when looking up the operands
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/// @arg syntax - The syntax to use, according to LLVM's enumeration
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void populateOperandOrder(CompoundConstantEmitter *operandOrder,
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const CodeGenInstruction &inst,
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unsigned syntax) {
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unsigned int numArgs = 0;
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AsmWriterInst awInst(inst, syntax, -1, -1);
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std::vector<AsmWriterOperand>::iterator operandIterator;
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for (operandIterator = awInst.Operands.begin();
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operandIterator != awInst.Operands.end();
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++operandIterator) {
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if (operandIterator->OperandType ==
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AsmWriterOperand::isMachineInstrOperand) {
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operandOrder->addEntry(
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new LiteralConstantEmitter(operandIterator->CGIOpNo));
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numArgs++;
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}
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}
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}
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/////////////////////////////////////////////////////
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// Support functions for handling X86 instructions //
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/////////////////////////////////////////////////////
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#define SET(flag) { type->set(flag); return 0; }
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#define REG(str) if (name == str) SET("kOperandTypeRegister");
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#define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
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#define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
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#define IMM(str) if (name == str) SET("kOperandTypeImmediate");
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#define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
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/// X86TypeFromOpName - Processes the name of a single X86 operand (which is
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/// actually its type) and translates it into an operand type
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///
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/// @arg flags - The type object to set
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/// @arg name - The name of the operand
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static int X86TypeFromOpName(LiteralConstantEmitter *type,
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const std::string &name) {
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REG("GR8");
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REG("GR8_NOREX");
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REG("GR16");
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REG("GR32");
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REG("GR32_NOREX");
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REG("GR32_TC");
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REG("FR32");
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REG("RFP32");
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REG("GR64");
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REG("GR64_TC");
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REG("FR64");
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REG("VR64");
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REG("RFP64");
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REG("RFP80");
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REG("VR128");
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REG("VR256");
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REG("RST");
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REG("SEGMENT_REG");
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REG("DEBUG_REG");
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REG("CONTROL_REG");
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IMM("i8imm");
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IMM("i16imm");
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IMM("i16i8imm");
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IMM("i32imm");
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IMM("i32i8imm");
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IMM("i64imm");
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IMM("i64i8imm");
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IMM("i64i32imm");
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IMM("SSECC");
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// all R, I, R, I, R
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MEM("i8mem");
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MEM("i8mem_NOREX");
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MEM("i16mem");
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MEM("i32mem");
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MEM("i32mem_TC");
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MEM("f32mem");
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MEM("ssmem");
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MEM("opaque32mem");
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MEM("opaque48mem");
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MEM("i64mem");
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MEM("i64mem_TC");
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MEM("f64mem");
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MEM("sdmem");
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MEM("f80mem");
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MEM("opaque80mem");
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MEM("i128mem");
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MEM("i256mem");
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MEM("f128mem");
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MEM("f256mem");
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MEM("opaque512mem");
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// all R, I, R, I
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LEA("lea32mem");
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LEA("lea64_32mem");
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LEA("lea64mem");
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// all I
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PCR("i16imm_pcrel");
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PCR("i32imm_pcrel");
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PCR("i64i32imm_pcrel");
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PCR("brtarget8");
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PCR("offset8");
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PCR("offset16");
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PCR("offset32");
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PCR("offset64");
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PCR("brtarget");
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PCR("uncondbrtarget");
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PCR("bltarget");
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// all I, ARM mode only, conditional/unconditional
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PCR("br_target");
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PCR("bl_target");
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return 1;
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}
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#undef REG
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#undef MEM
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#undef LEA
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#undef IMM
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#undef PCR
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#undef SET
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/// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
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/// the appropriate flags to their descriptors
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///
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/// @operandFlags - A reference the array of operand flag objects
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/// @inst - The instruction to use as a source of information
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static void X86PopulateOperands(
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LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
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const CodeGenInstruction &inst) {
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if (!inst.TheDef->isSubClassOf("X86Inst"))
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return;
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unsigned int index;
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unsigned int numOperands = inst.Operands.size();
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for (index = 0; index < numOperands; ++index) {
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const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
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Record &rec = *operandInfo.Rec;
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if (X86TypeFromOpName(operandTypes[index], rec.getName()) &&
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!rec.isSubClassOf("PointerLikeRegClass")) {
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errs() << "Operand type: " << rec.getName().c_str() << "\n";
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errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
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errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
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llvm_unreachable("Unhandled type");
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}
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}
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}
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/// decorate1 - Decorates a named operand with a new flag
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///
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/// @operandFlags - The array of operand flag objects, which don't have names
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/// @inst - The CodeGenInstruction, which provides a way to translate
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/// between names and operand indices
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/// @opName - The name of the operand
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/// @flag - The name of the flag to add
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static inline void decorate1(
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FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
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const CodeGenInstruction &inst,
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const char *opName,
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const char *opFlag) {
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unsigned opIndex;
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opIndex = inst.Operands.getOperandNamed(std::string(opName));
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operandFlags[opIndex]->addEntry(opFlag);
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}
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#define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
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#define MOV(source, target) { \
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instType.set("kInstructionTypeMove"); \
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DECORATE1(source, "kOperandFlagSource"); \
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DECORATE1(target, "kOperandFlagTarget"); \
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}
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#define BRANCH(target) { \
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instType.set("kInstructionTypeBranch"); \
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DECORATE1(target, "kOperandFlagTarget"); \
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}
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#define PUSH(source) { \
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instType.set("kInstructionTypePush"); \
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DECORATE1(source, "kOperandFlagSource"); \
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}
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#define POP(target) { \
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instType.set("kInstructionTypePop"); \
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DECORATE1(target, "kOperandFlagTarget"); \
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}
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#define CALL(target) { \
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instType.set("kInstructionTypeCall"); \
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DECORATE1(target, "kOperandFlagTarget"); \
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}
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#define RETURN() { \
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instType.set("kInstructionTypeReturn"); \
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}
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/// X86ExtractSemantics - Performs various checks on the name of an X86
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/// instruction to determine what sort of an instruction it is and then adds
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/// the appropriate flags to the instruction and its operands
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///
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/// @arg instType - A reference to the type for the instruction as a whole
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/// @arg operandFlags - A reference to the array of operand flag object pointers
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/// @arg inst - A reference to the original instruction
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static void X86ExtractSemantics(
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LiteralConstantEmitter &instType,
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FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
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const CodeGenInstruction &inst) {
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const std::string &name = inst.TheDef->getName();
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if (name.find("MOV") != name.npos) {
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if (name.find("MOV_V") != name.npos) {
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// ignore (this is a pseudoinstruction)
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} else if (name.find("MASK") != name.npos) {
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// ignore (this is a masking move)
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} else if (name.find("r0") != name.npos) {
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// ignore (this is a pseudoinstruction)
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} else if (name.find("PS") != name.npos ||
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name.find("PD") != name.npos) {
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// ignore (this is a shuffling move)
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} else if (name.find("MOVS") != name.npos) {
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// ignore (this is a string move)
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} else if (name.find("_F") != name.npos) {
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// TODO handle _F moves to ST(0)
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} else if (name.find("a") != name.npos) {
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// TODO handle moves to/from %ax
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} else if (name.find("CMOV") != name.npos) {
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MOV("src2", "dst");
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} else if (name.find("PC") != name.npos) {
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MOV("label", "reg")
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} else {
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MOV("src", "dst");
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}
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}
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if (name.find("JMP") != name.npos ||
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name.find("J") == 0) {
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if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
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BRANCH("off");
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} else {
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BRANCH("dst");
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}
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}
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if (name.find("PUSH") != name.npos) {
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if (name.find("CS") != name.npos ||
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name.find("DS") != name.npos ||
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name.find("ES") != name.npos ||
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name.find("FS") != name.npos ||
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name.find("GS") != name.npos ||
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name.find("SS") != name.npos) {
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instType.set("kInstructionTypePush");
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// TODO add support for fixed operands
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} else if (name.find("F") != name.npos) {
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// ignore (this pushes onto the FP stack)
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} else if (name.find("A") != name.npos) {
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// ignore (pushes all GP registoers onto the stack)
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} else if (name[name.length() - 1] == 'm') {
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PUSH("src");
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} else if (name.find("i") != name.npos) {
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PUSH("imm");
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} else {
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PUSH("reg");
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}
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}
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if (name.find("POP") != name.npos) {
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if (name.find("POPCNT") != name.npos) {
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// ignore (not a real pop)
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} else if (name.find("CS") != name.npos ||
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name.find("DS") != name.npos ||
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name.find("ES") != name.npos ||
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name.find("FS") != name.npos ||
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name.find("GS") != name.npos ||
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name.find("SS") != name.npos) {
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instType.set("kInstructionTypePop");
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// TODO add support for fixed operands
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} else if (name.find("F") != name.npos) {
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// ignore (this pops from the FP stack)
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} else if (name.find("A") != name.npos) {
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// ignore (pushes all GP registoers onto the stack)
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} else if (name[name.length() - 1] == 'm') {
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POP("dst");
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} else {
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POP("reg");
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}
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}
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if (name.find("CALL") != name.npos) {
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if (name.find("ADJ") != name.npos) {
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// ignore (not a call)
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} else if (name.find("SYSCALL") != name.npos) {
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// ignore (doesn't go anywhere we know about)
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|
} else if (name.find("VMCALL") != name.npos) {
|
|
// ignore (rather different semantics than a regular call)
|
|
} else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
|
|
CALL("off");
|
|
} else {
|
|
CALL("dst");
|
|
}
|
|
}
|
|
|
|
if (name.find("RET") != name.npos) {
|
|
RETURN();
|
|
}
|
|
}
|
|
|
|
#undef MOV
|
|
#undef BRANCH
|
|
#undef PUSH
|
|
#undef POP
|
|
#undef CALL
|
|
#undef RETURN
|
|
|
|
/////////////////////////////////////////////////////
|
|
// Support functions for handling ARM instructions //
|
|
/////////////////////////////////////////////////////
|
|
|
|
#define SET(flag) { type->set(flag); return 0; }
|
|
|
|
#define REG(str) if (name == str) SET("kOperandTypeRegister");
|
|
#define IMM(str) if (name == str) SET("kOperandTypeImmediate");
|
|
|
|
#define MISC(str, type) if (name == str) SET(type);
|
|
|
|
/// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
|
|
/// actually its type) and translates it into an operand type
|
|
///
|
|
/// @arg type - The type object to set
|
|
/// @arg name - The name of the operand
|
|
static int ARMFlagFromOpName(LiteralConstantEmitter *type,
|
|
const std::string &name) {
|
|
REG("GPR");
|
|
REG("rGPR");
|
|
REG("tcGPR");
|
|
REG("cc_out");
|
|
REG("s_cc_out");
|
|
REG("tGPR");
|
|
REG("DPR");
|
|
REG("DPR_VFP2");
|
|
REG("DPR_8");
|
|
REG("SPR");
|
|
REG("QPR");
|
|
REG("QQPR");
|
|
REG("QQQQPR");
|
|
|
|
IMM("i32imm");
|
|
IMM("i32imm_hilo16");
|
|
IMM("bf_inv_mask_imm");
|
|
IMM("lsb_pos_imm");
|
|
IMM("width_imm");
|
|
IMM("jtblock_operand");
|
|
IMM("nohash_imm");
|
|
IMM("p_imm");
|
|
IMM("c_imm");
|
|
IMM("imod_op");
|
|
IMM("iflags_op");
|
|
IMM("cpinst_operand");
|
|
IMM("setend_op");
|
|
IMM("cps_opt");
|
|
IMM("vfp_f64imm");
|
|
IMM("vfp_f32imm");
|
|
IMM("memb_opt");
|
|
IMM("msr_mask");
|
|
IMM("neg_zero");
|
|
IMM("imm0_31");
|
|
IMM("imm0_31_m1");
|
|
IMM("nModImm");
|
|
IMM("imm0_4095");
|
|
IMM("jt2block_operand");
|
|
IMM("t_imm_s4");
|
|
IMM("pclabel");
|
|
IMM("adrlabel");
|
|
IMM("t_adrlabel");
|
|
IMM("t2adrlabel");
|
|
IMM("shift_imm");
|
|
IMM("neon_vcvt_imm32");
|
|
IMM("shr_imm8");
|
|
IMM("shr_imm16");
|
|
IMM("shr_imm32");
|
|
IMM("shr_imm64");
|
|
|
|
MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
|
|
MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?
|
|
MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ?
|
|
MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ?
|
|
MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ?
|
|
MISC("bltarget", "kOperandTypeARMBranchTarget"); // ?
|
|
|
|
MISC("br_target", "kOperandTypeARMBranchTarget"); // ?
|
|
MISC("bl_target", "kOperandTypeARMBranchTarget"); // ?
|
|
|
|
MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ?
|
|
MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ?
|
|
MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I
|
|
MISC("shift_so_reg", "kOperandTypeARMSoReg"); // R, R, I
|
|
MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
|
|
MISC("so_imm", "kOperandTypeARMSoImm"); // I
|
|
MISC("rot_imm", "kOperandTypeARMRotImm"); // I
|
|
MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
|
|
MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
|
|
MISC("pred", "kOperandTypeARMPredicate"); // I, R
|
|
MISC("it_pred", "kOperandTypeARMPredicate"); // I
|
|
MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I
|
|
MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I
|
|
MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
|
|
MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I
|
|
MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
|
|
MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
|
|
MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I
|
|
MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
|
|
MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
|
|
MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
|
|
MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I
|
|
MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
|
|
MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
|
|
MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ...
|
|
MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ...
|
|
MISC("it_mask", "kOperandTypeThumbITMask"); // I
|
|
MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
|
|
MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
|
|
MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
|
|
MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
|
|
MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
|
|
MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
|
|
// R, I
|
|
MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
|
|
MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS"); // R, R
|
|
MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS"); // R, R
|
|
MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS"); // R, R
|
|
MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS"); // R, I
|
|
MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS"); // R, I
|
|
MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS"); // R, I
|
|
MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
|
|
MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
|
|
MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I
|
|
|
|
return 1;
|
|
}
|
|
|
|
#undef SOREG
|
|
#undef SOIMM
|
|
#undef PRED
|
|
#undef REG
|
|
#undef MEM
|
|
#undef LEA
|
|
#undef IMM
|
|
#undef PCR
|
|
|
|
#undef SET
|
|
|
|
/// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
|
|
/// the appropriate flags to their descriptors
|
|
///
|
|
/// @operandFlags - A reference the array of operand flag objects
|
|
/// @inst - The instruction to use as a source of information
|
|
static void ARMPopulateOperands(
|
|
LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
|
|
const CodeGenInstruction &inst) {
|
|
if (!inst.TheDef->isSubClassOf("InstARM") &&
|
|
!inst.TheDef->isSubClassOf("InstThumb"))
|
|
return;
|
|
|
|
unsigned int index;
|
|
unsigned int numOperands = inst.Operands.size();
|
|
|
|
if (numOperands > EDIS_MAX_OPERANDS) {
|
|
errs() << "numOperands == " << numOperands << " > " <<
|
|
EDIS_MAX_OPERANDS << '\n';
|
|
llvm_unreachable("Too many operands");
|
|
}
|
|
|
|
for (index = 0; index < numOperands; ++index) {
|
|
const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
|
|
Record &rec = *operandInfo.Rec;
|
|
|
|
if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
|
|
errs() << "Operand type: " << rec.getName() << '\n';
|
|
errs() << "Operand name: " << operandInfo.Name << '\n';
|
|
errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
|
|
llvm_unreachable("Unhandled type");
|
|
}
|
|
}
|
|
}
|
|
|
|
#define BRANCH(target) { \
|
|
instType.set("kInstructionTypeBranch"); \
|
|
DECORATE1(target, "kOperandFlagTarget"); \
|
|
}
|
|
|
|
/// ARMExtractSemantics - Performs various checks on the name of an ARM
|
|
/// instruction to determine what sort of an instruction it is and then adds
|
|
/// the appropriate flags to the instruction and its operands
|
|
///
|
|
/// @arg instType - A reference to the type for the instruction as a whole
|
|
/// @arg operandTypes - A reference to the array of operand type object pointers
|
|
/// @arg operandFlags - A reference to the array of operand flag object pointers
|
|
/// @arg inst - A reference to the original instruction
|
|
static void ARMExtractSemantics(
|
|
LiteralConstantEmitter &instType,
|
|
LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
|
|
FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
|
|
const CodeGenInstruction &inst) {
|
|
const std::string &name = inst.TheDef->getName();
|
|
|
|
if (name == "tBcc" ||
|
|
name == "tB" ||
|
|
name == "t2Bcc" ||
|
|
name == "Bcc" ||
|
|
name == "tCBZ" ||
|
|
name == "tCBNZ") {
|
|
BRANCH("target");
|
|
}
|
|
|
|
if (name == "tBLr9" ||
|
|
name == "BLr9_pred" ||
|
|
name == "tBLXi_r9" ||
|
|
name == "tBLXr_r9" ||
|
|
name == "BLXr9" ||
|
|
name == "t2BXJ" ||
|
|
name == "BXJ") {
|
|
BRANCH("func");
|
|
|
|
unsigned opIndex;
|
|
opIndex = inst.Operands.getOperandNamed("func");
|
|
if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
|
|
operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
|
|
}
|
|
}
|
|
|
|
#undef BRANCH
|
|
|
|
/// populateInstInfo - Fills an array of InstInfos with information about each
|
|
/// instruction in a target
|
|
///
|
|
/// @arg infoArray - The array of InstInfo objects to populate
|
|
/// @arg target - The CodeGenTarget to use as a source of instructions
|
|
static void populateInstInfo(CompoundConstantEmitter &infoArray,
|
|
CodeGenTarget &target) {
|
|
const std::vector<const CodeGenInstruction*> &numberedInstructions =
|
|
target.getInstructionsByEnumValue();
|
|
|
|
unsigned int index;
|
|
unsigned int numInstructions = numberedInstructions.size();
|
|
|
|
for (index = 0; index < numInstructions; ++index) {
|
|
const CodeGenInstruction& inst = *numberedInstructions[index];
|
|
|
|
CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
|
|
infoArray.addEntry(infoStruct);
|
|
|
|
LiteralConstantEmitter *instType = new LiteralConstantEmitter;
|
|
infoStruct->addEntry(instType);
|
|
|
|
LiteralConstantEmitter *numOperandsEmitter =
|
|
new LiteralConstantEmitter(inst.Operands.size());
|
|
infoStruct->addEntry(numOperandsEmitter);
|
|
|
|
CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
|
|
infoStruct->addEntry(operandTypeArray);
|
|
|
|
LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
|
|
|
|
CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
|
|
infoStruct->addEntry(operandFlagArray);
|
|
|
|
FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
|
|
|
|
for (unsigned operandIndex = 0;
|
|
operandIndex < EDIS_MAX_OPERANDS;
|
|
++operandIndex) {
|
|
operandTypes[operandIndex] = new LiteralConstantEmitter;
|
|
operandTypeArray->addEntry(operandTypes[operandIndex]);
|
|
|
|
operandFlags[operandIndex] = new FlagsConstantEmitter;
|
|
operandFlagArray->addEntry(operandFlags[operandIndex]);
|
|
}
|
|
|
|
unsigned numSyntaxes = 0;
|
|
|
|
if (target.getName() == "X86") {
|
|
X86PopulateOperands(operandTypes, inst);
|
|
X86ExtractSemantics(*instType, operandFlags, inst);
|
|
numSyntaxes = 2;
|
|
}
|
|
else if (target.getName() == "ARM") {
|
|
ARMPopulateOperands(operandTypes, inst);
|
|
ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
|
|
numSyntaxes = 1;
|
|
}
|
|
|
|
CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
|
|
|
|
infoStruct->addEntry(operandOrderArray);
|
|
|
|
for (unsigned syntaxIndex = 0;
|
|
syntaxIndex < EDIS_MAX_SYNTAXES;
|
|
++syntaxIndex) {
|
|
CompoundConstantEmitter *operandOrder =
|
|
new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
|
|
|
|
operandOrderArray->addEntry(operandOrder);
|
|
|
|
if (syntaxIndex < numSyntaxes) {
|
|
populateOperandOrder(operandOrder, inst, syntaxIndex);
|
|
}
|
|
}
|
|
|
|
infoStruct = NULL;
|
|
}
|
|
}
|
|
|
|
static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
|
|
EnumEmitter operandTypes("OperandTypes");
|
|
operandTypes.addEntry("kOperandTypeNone");
|
|
operandTypes.addEntry("kOperandTypeImmediate");
|
|
operandTypes.addEntry("kOperandTypeRegister");
|
|
operandTypes.addEntry("kOperandTypeX86Memory");
|
|
operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
|
|
operandTypes.addEntry("kOperandTypeX86PCRelative");
|
|
operandTypes.addEntry("kOperandTypeARMBranchTarget");
|
|
operandTypes.addEntry("kOperandTypeARMSoReg");
|
|
operandTypes.addEntry("kOperandTypeARMSoImm");
|
|
operandTypes.addEntry("kOperandTypeARMRotImm");
|
|
operandTypes.addEntry("kOperandTypeARMSoImm2Part");
|
|
operandTypes.addEntry("kOperandTypeARMPredicate");
|
|
operandTypes.addEntry("kOperandTypeAddrModeImm12");
|
|
operandTypes.addEntry("kOperandTypeLdStSOReg");
|
|
operandTypes.addEntry("kOperandTypeARMAddrMode2");
|
|
operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
|
|
operandTypes.addEntry("kOperandTypeARMAddrMode3");
|
|
operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
|
|
operandTypes.addEntry("kOperandTypeARMLdStmMode");
|
|
operandTypes.addEntry("kOperandTypeARMAddrMode5");
|
|
operandTypes.addEntry("kOperandTypeARMAddrMode6");
|
|
operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
|
|
operandTypes.addEntry("kOperandTypeARMAddrModePC");
|
|
operandTypes.addEntry("kOperandTypeARMRegisterList");
|
|
operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
|
|
operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
|
|
operandTypes.addEntry("kOperandTypeARMTBAddrMode");
|
|
operandTypes.addEntry("kOperandTypeThumbITMask");
|
|
operandTypes.addEntry("kOperandTypeThumbAddrModeRegS");
|
|
operandTypes.addEntry("kOperandTypeThumbAddrModeImmS");
|
|
operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
|
|
operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
|
|
operandTypes.addEntry("kOperandTypeThumbAddrModePC");
|
|
operandTypes.addEntry("kOperandTypeThumb2SoReg");
|
|
operandTypes.addEntry("kOperandTypeThumb2SoImm");
|
|
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
|
|
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
|
|
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
|
|
operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
|
|
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
|
|
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
|
|
operandTypes.emit(o, i);
|
|
|
|
o << "\n";
|
|
|
|
EnumEmitter operandFlags("OperandFlags");
|
|
operandFlags.addEntry("kOperandFlagSource");
|
|
operandFlags.addEntry("kOperandFlagTarget");
|
|
operandFlags.emitAsFlags(o, i);
|
|
|
|
o << "\n";
|
|
|
|
EnumEmitter instructionTypes("InstructionTypes");
|
|
instructionTypes.addEntry("kInstructionTypeNone");
|
|
instructionTypes.addEntry("kInstructionTypeMove");
|
|
instructionTypes.addEntry("kInstructionTypeBranch");
|
|
instructionTypes.addEntry("kInstructionTypePush");
|
|
instructionTypes.addEntry("kInstructionTypePop");
|
|
instructionTypes.addEntry("kInstructionTypeCall");
|
|
instructionTypes.addEntry("kInstructionTypeReturn");
|
|
instructionTypes.emit(o, i);
|
|
|
|
o << "\n";
|
|
}
|
|
|
|
void EDEmitter::run(raw_ostream &o) {
|
|
unsigned int i = 0;
|
|
|
|
CompoundConstantEmitter infoArray;
|
|
CodeGenTarget target(Records);
|
|
|
|
populateInstInfo(infoArray, target);
|
|
|
|
emitCommonEnums(o, i);
|
|
|
|
o << "namespace {\n";
|
|
|
|
o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
|
|
infoArray.emit(o, i);
|
|
o << ";" << "\n";
|
|
|
|
o << "}\n";
|
|
}
|