mirror of
https://github.com/c64scene-ar/llvm-6502.git
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596cfabbc4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226480 91177308-0d34-0410-b5e6-96231b3b80d8
142 lines
3.7 KiB
LLVM
142 lines
3.7 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Verify that ALU32 - add, or, and, sub, combine intrinsics
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; are lowered to the right instructions.
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@e = external global i1
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@b = external global i8
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@d = external global i32
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@c = external global i64
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test1(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}sub(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test2(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.sub(i32 %a, i32 %b)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}and(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test3(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}or(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test4(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.or(i32 %a, i32 %b)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}xor(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test5(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.xor(i32 %a, i32 %b)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}combine(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define void @test6(i32 %a, i32 %b) #0 {
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entry:
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%0 = tail call i64 @llvm.hexagon.A2.combinew(i32 %a, i32 %b)
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store i64 %0, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}#-31849)
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define void @test7(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.addi(i32 %a, i32 -31849)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}and(r{{[0-9]+}}{{ *}},{{ *}}#-512)
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define void @test8(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.andir(i32 %a, i32 -512)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}or(r{{[0-9]+}}{{ *}},{{ *}}#511)
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define void @test9(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.orir(i32 %a, i32 511)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}sub(#508{{ *}},{{ *}}r{{[0-9]+}})
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define void @test10(i32 %a) #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.A2.subri(i32 508, i32 %a)
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%conv = sext i32 %0 to i64
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store i64 %conv, i64* @c, align 8
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ret void
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}
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; CHECK: r{{[0-9]+}}.l{{ *}}={{ *}}#48242
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define void @test11() #0 {
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entry:
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%0 = load i32* @d, align 4
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%1 = tail call i32 @llvm.hexagon.A2.tfril(i32 %0, i32 48242)
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store i32 %1, i32* @d, align 4
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ret void
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}
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; CHECK: r{{[0-9]+}}.h{{ *}}={{ *}}#50826
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define void @test12() #0 {
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entry:
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%0 = load i32* @d, align 4
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%1 = tail call i32 @llvm.hexagon.A2.tfrih(i32 %0, i32 50826)
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store i32 %1, i32* @d, align 4
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ret void
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}
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declare i32 @llvm.hexagon.A2.add(i32, i32) #1
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declare i32 @llvm.hexagon.A2.sub(i32, i32) #1
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declare i32 @llvm.hexagon.A2.and(i32, i32) #1
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declare i32 @llvm.hexagon.A2.or(i32, i32) #1
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declare i32 @llvm.hexagon.A2.xor(i32, i32) #1
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declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
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declare i32 @llvm.hexagon.A2.addi(i32, i32) #1
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declare i32 @llvm.hexagon.A2.andir(i32, i32) #1
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declare i32 @llvm.hexagon.A2.orir(i32, i32) #1
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declare i32 @llvm.hexagon.A2.subri(i32, i32)
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declare i32 @llvm.hexagon.A2.tfril(i32, i32) #1
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declare i32 @llvm.hexagon.A2.tfrih(i32, i32) #1
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