mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
2.9 KiB
TableGen
92 lines
2.9 KiB
TableGen
//===- XCoreRegisterInfo.td - XCore Register defs ----------*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Declarations that describe the XCore register file
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class XCoreReg<string n> : Register<n> {
|
|
field bits<4> Num;
|
|
let Namespace = "XCore";
|
|
}
|
|
|
|
// Registers are identified with 4-bit ID numbers.
|
|
// Ri - 32-bit integer registers
|
|
class Ri<bits<4> num, string n> : XCoreReg<n> {
|
|
let Num = num;
|
|
}
|
|
|
|
// CPU registers
|
|
def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
|
|
def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
|
|
def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
|
|
def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
|
|
def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
|
|
def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
|
|
def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
|
|
def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
|
|
def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
|
|
def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
|
|
def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
|
|
def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
|
|
def CP : Ri<12, "cp">, DwarfRegNum<[12]>;
|
|
def DP : Ri<13, "dp">, DwarfRegNum<[13]>;
|
|
def SP : Ri<14, "sp">, DwarfRegNum<[14]>;
|
|
def LR : Ri<15, "lr">, DwarfRegNum<[15]>;
|
|
|
|
// Register classes.
|
|
//
|
|
def GRRegs : RegisterClass<"XCore", [i32], 32,
|
|
// Return values and arguments
|
|
[R0, R1, R2, R3,
|
|
// Not preserved across procedure calls
|
|
R11,
|
|
// Callee save
|
|
R4, R5, R6, R7, R8, R9, R10]> {
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
GRRegsClass::iterator
|
|
GRRegsClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
return begin();
|
|
}
|
|
GRRegsClass::iterator
|
|
GRRegsClass::allocation_order_end(const MachineFunction &MF) const {
|
|
const TargetMachine &TM = MF.getTarget();
|
|
const TargetFrameLowering *TFI = TM.getFrameLowering();
|
|
if (TFI->hasFP(MF))
|
|
return end()-1; // don't allocate R10
|
|
else
|
|
return end();
|
|
}
|
|
}];
|
|
}
|
|
|
|
def RRegs : RegisterClass<"XCore", [i32], 32,
|
|
// Reserved
|
|
[CP, DP, SP, LR]> {
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
RRegsClass::iterator
|
|
RRegsClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
return begin();
|
|
}
|
|
RRegsClass::iterator
|
|
RRegsClass::allocation_order_end(const MachineFunction &MF) const {
|
|
// No allocatable registers
|
|
return begin();
|
|
}
|
|
}];
|
|
}
|