mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-25 19:29:53 +00:00
TableGen will not combine nested list 'let' bindings into a single list, and instead uses only the inner scope. As a result, several instruction definitions were missing implicit register defs that were in outer scopes. This de-nests these scopes and makes all instructions have only one let binding which sets implicit register definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179392 91177308-0d34-0410-b5e6-96231b3b80d8