Hal Finkel 59889f7f49 Cleanup and improve PPC fsel generation ... First, we should not cheat: fsel-based lowering of select_cc is a finite-math-only optimization (the ISA manual, section F.3 of v2.06, makes this clear, as does a note in our own README). This also adds fsel-based lowering of EQ and NE condition codes. As it turned out, fsel generation was covered by a grand total of zero regression test cases. I've added some test cases to cover the existing behavior (which is now finite-math only), as well as the new EQ cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179000 91177308-0d34-0410-b5e6-96231b3b80d8		2013-04-07 22:11:09 +00:00
..
AArch64	Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings	2013-03-26 18:56:54 +00:00
ARM	Reverting 178851 as it broke buildbots	2013-04-05 16:39:53 +00:00
CPP
Generic	XFAIL some of the generic CodeGen tests for Hexagon.	2013-03-25 21:04:16 +00:00
Hexagon	Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.	2013-03-28 19:34:49 +00:00
Inputs	Revert "Adding DIImportedModules to DIScopes."	2013-03-28 02:44:59 +00:00
MBlaze
Mips	[mips] Small update to the implementation of eh.return for Mips.	2013-04-02 23:02:07 +00:00
MSP430
NVPTX	[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.	2013-03-30 14:29:30 +00:00
PowerPC	Cleanup and improve PPC fsel generation	2013-04-07 22:11:09 +00:00
R600	R600/SI: Add support for buffer stores v2	2013-04-05 23:31:51 +00:00
SI
SPARC	Implement LowerCall_64 for the SPARC v9 64-bit ABI.	2013-04-07 19:10:57 +00:00
Thumb	Revert "Adding DIImportedModules to DIScopes."	2013-03-28 02:44:59 +00:00
Thumb2
X86	Make the test/CodeGen/X86/win32_sret.ll reliable on any CPU by explicitly specifying the -mcpu	2013-04-05 17:05:56 +00:00
XCore