Evan Cheng 599a6a88ce Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8		2009-03-04 01:41:49 +00:00
..
CallingConvLower.cpp
CMakeLists.txt
DAGCombiner.cpp	Fix a problem with DAGCombine on 64b targets where folding	2009-03-01 23:44:07 +00:00
FastISel.cpp
LegalizeDAG.cpp
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorTypes.cpp
Makefile
ScheduleDAGFast.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp	Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs.	2009-03-04 01:41:49 +00:00
ScheduleDAGSDNodes.cpp
ScheduleDAGSDNodes.h
ScheduleDAGSDNodesEmit.cpp
SelectionDAG.cpp	Generalize BuildVectorSDNode::isConstantSplat to use APInts and handle	2009-03-02 23:24:16 +00:00
SelectionDAGBuild.cpp
SelectionDAGBuild.h
SelectionDAGISel.cpp
SelectionDAGPrinter.cpp
TargetLowering.cpp	The DAG combiner was performing a BT combine. The BT combine had a value of -1,	2009-03-04 00:18:06 +00:00