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https://github.com/c64scene-ar/llvm-6502.git
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b9803a8fa6
load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
3.3 KiB
C++
120 lines
3.3 KiB
C++
//===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "thumb2-it"
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#include "ARM.h"
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#include "ARMMachineFunctionInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumITs, "Number of IT blocks inserted");
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namespace {
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struct Thumb2ITBlockPass : public MachineFunctionPass {
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static char ID;
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Thumb2ITBlockPass() : MachineFunctionPass(&ID) {}
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const Thumb2InstrInfo *TII;
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ARMFunctionInfo *AFI;
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "Thumb IT blocks insertion pass";
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}
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private:
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bool InsertITBlocks(MachineBasicBlock &MBB);
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};
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char Thumb2ITBlockPass::ID = 0;
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}
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static ARMCC::CondCodes getPredicate(const MachineInstr *MI, unsigned &PredReg){
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unsigned Opc = MI->getOpcode();
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if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
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return ARMCC::AL;
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return llvm::getInstrPredicate(MI, PredReg);
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}
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bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineInstr *MI = &*MBBI;
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DebugLoc dl = MI->getDebugLoc();
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unsigned PredReg = 0;
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ARMCC::CondCodes CC = getPredicate(MI, PredReg);
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if (CC == ARMCC::AL) {
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++MBBI;
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continue;
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}
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// Insert an IT instruction.
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
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.addImm(CC);
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++MBBI;
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// Finalize IT mask.
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ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
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unsigned Mask = 0, Pos = 3;
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// Branches, including tricky ones like LDM_RET, need to end an IT
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// block so check the instruction we just put in the block.
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while (MBBI != E && Pos &&
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(!MI->getDesc().isBranch() && !MI->getDesc().isReturn())) {
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MachineInstr *NMI = &*MBBI;
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MI = NMI;
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DebugLoc ndl = NMI->getDebugLoc();
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unsigned NPredReg = 0;
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ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
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if (NCC == OCC) {
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Mask |= (1 << Pos);
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} else if (NCC != CC)
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break;
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--Pos;
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++MBBI;
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}
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Mask |= (1 << Pos);
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MIB.addImm(Mask);
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Modified = true;
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++NumITs;
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}
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return Modified;
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}
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bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
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const TargetMachine &TM = Fn.getTarget();
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AFI = Fn.getInfo<ARMFunctionInfo>();
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TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
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if (!AFI->isThumbFunction())
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return false;
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bool Modified = false;
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for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
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++MFI) {
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MachineBasicBlock &MBB = *MFI;
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Modified |= InsertITBlocks(MBB);
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}
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return Modified;
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}
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/// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
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/// insertion pass.
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FunctionPass *llvm::createThumb2ITBlockPass() {
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return new Thumb2ITBlockPass();
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}
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