llvm-6502/lib/Target/PowerPC/PPCScheduleG3.td
Hal Finkel 8dc440a46a Split several PPC instruction classes.
Slight reorganisation of PPC instruction classes for scheduling. No
functionality change for existing subtargets.
 - Clearly separate load/store-with-update instructions from regular loads and stores.
 - Split IntRotateD -> IntRotateD and IntRotateDI
 - Split out fsub and fadd from FPGeneral -> FPAddSub
 - Update existing itineraries

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 02:49:14 +00:00

72 lines
3.5 KiB
TableGen

//===-- PPCScheduleG3.td - PPC G3 Scheduling Definitions ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the G3 (750) processor.
//
//===----------------------------------------------------------------------===//
def G3Itineraries : ProcessorItineraries<
[IU1, IU2, FPU1, BPU, SRU, SLU], [], [
InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
InstrItinData<IntMFFS , [InstrStage<1, [FPU1]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
InstrItinData<BrCR , [InstrStage<1, [SRU]>]>,
InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>,
InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>,
InstrItinData<LdStDCBA , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLoad , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLoadUpd , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStStore , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStStoreUpd, [InstrStage<2, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTFD , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStSTFDU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLHAU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTWCX , [InstrStage<8, [SLU]>]>,
InstrItinData<LdStSync , [InstrStage<3, [SLU]>]>,
InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>,
InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>,
InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>,
InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>,
InstrItinData<SprTLBSYNC , [InstrStage<3, [SRU]>]>,
InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>,
InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>,
InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>,
InstrItinData<SprMFTB , [InstrStage<3, [SRU]>]>,
InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>,
InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>,
InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>,
InstrItinData<SprSC , [InstrStage<2, [SRU]>]>,
InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPAddSub , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>,
InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
InstrItinData<FPFused , [InstrStage<2, [FPU1]>]>,
InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>
]>;