mirror of
https://github.com/c64scene-ar/llvm-6502.git
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9ab0f25fc1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
1.9 KiB
C++
69 lines
1.9 KiB
C++
//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "ARMMachineFunctionInfo.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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using namespace llvm;
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ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI), RI(*this, STI) {
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}
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unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
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switch (Opc) {
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default: break;
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case ARM::LDR_PRE_IMM:
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case ARM::LDR_PRE_REG:
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case ARM::LDR_POST_IMM:
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case ARM::LDR_POST_REG:
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return ARM::LDRi12;
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case ARM::LDRH_PRE:
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case ARM::LDRH_POST:
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return ARM::LDRH;
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case ARM::LDRB_PRE_IMM:
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case ARM::LDRB_PRE_REG:
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case ARM::LDRB_POST_IMM:
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case ARM::LDRB_POST_REG:
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return ARM::LDRBi12;
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case ARM::LDRSH_PRE:
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case ARM::LDRSH_POST:
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return ARM::LDRSH;
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case ARM::LDRSB_PRE:
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case ARM::LDRSB_POST:
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return ARM::LDRSB;
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case ARM::STR_PRE_IMM:
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case ARM::STR_PRE_REG:
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case ARM::STR_POST_IMM:
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case ARM::STR_POST_REG:
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return ARM::STRi12;
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case ARM::STRH_PRE:
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case ARM::STRH_POST:
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return ARM::STRH;
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case ARM::STRB_PRE_IMM:
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case ARM::STRB_PRE_REG:
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case ARM::STRB_POST_IMM:
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case ARM::STRB_POST_REG:
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return ARM::STRBi12;
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}
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return 0;
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}
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