mirror of
https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
2.2 KiB
LLVM
75 lines
2.2 KiB
LLVM
; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
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define signext i8 @test_vmaxv_s8(<8 x i8> %a1) {
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; CHECK: test_vmaxv_s8
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; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
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%0 = trunc i32 %vmaxv.i to i8
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ret i8 %0
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}
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define signext i16 @test_vmaxv_s16(<4 x i16> %a1) {
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; CHECK: test_vmaxv_s16
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; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a1)
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%0 = trunc i32 %vmaxv.i to i16
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ret i16 %0
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}
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define i32 @test_vmaxv_s32(<2 x i32> %a1) {
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; CHECK: test_vmaxv_s32
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; 2 x i32 is not supported by the ISA, thus, this is a special case
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; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v0, v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a1)
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ret i32 %vmaxv.i
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}
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define signext i8 @test_vmaxvq_s8(<16 x i8> %a1) {
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; CHECK: test_vmaxvq_s8
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; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a1)
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%0 = trunc i32 %vmaxv.i to i8
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ret i8 %0
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}
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define signext i16 @test_vmaxvq_s16(<8 x i16> %a1) {
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; CHECK: test_vmaxvq_s16
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; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a1)
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%0 = trunc i32 %vmaxv.i to i16
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ret i16 %0
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}
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define i32 @test_vmaxvq_s32(<4 x i32> %a1) {
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; CHECK: test_vmaxvq_s32
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; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v0
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; CHECK-NEXT: fmov w0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a1)
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ret i32 %vmaxv.i
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}
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declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
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declare i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32>)
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declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)
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