mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-26 21:32:10 +00:00
d0dbe02fd2
The C and C++ semantics for compare_exchange require it to return a bool
indicating success. This gets mapped to LLVM IR which follows each cmpxchg with
an icmp of the value loaded against the desired value.
When lowered to ldxr/stxr loops, this extra comparison is redundant: its
results are implicit in the control-flow of the function.
This commit makes two changes: it replaces that icmp with appropriate PHI
nodes, and then makes sure earlyCSE is called after expansion to actually make
use of the opportunities revealed.
I've also added -{arm,aarch64}-enable-atomic-tidy options, so that
existing fragile tests aren't perturbed too much by the change. Many
of them either rely on undef/unreachable too pervasively to be
restored to something well-defined (particularly while making sure
they test the same obscure assert from many years ago), or depend on a
particular CFG shape, which is disrupted by SimplifyCFG.
rdar://problem/16227836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209883 91177308-0d34-0410-b5e6-96231b3b80d8
525 lines
14 KiB
LLVM
525 lines
14 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-atomic-cfg-tidy=0 | FileCheck %s
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;
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; Get the actual value of the overflow bit.
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;
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define i1 @saddo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: saddo.i32
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; CHECK: adds w8, w0, w1
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; CHECK-NEXT: cset w0, vs
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define i1 @saddo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: saddo.i64
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; CHECK: adds x8, x0, x1
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; CHECK-NEXT: cset w0, vs
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: uaddo.i32
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; CHECK: adds w8, w0, w1
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; CHECK-NEXT: cset w0, hs
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: uaddo.i64
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; CHECK: adds x8, x0, x1
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; CHECK-NEXT: cset w0, hs
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define i1 @ssubo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: ssubo.i32
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; CHECK: subs w8, w0, w1
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; CHECK-NEXT: cset w0, vs
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%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: ssubo.i64
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; CHECK: subs x8, x0, x1
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; CHECK-NEXT: cset w0, vs
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%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: usubo.i32
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; CHECK: subs w8, w0, w1
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; CHECK-NEXT: cset w0, lo
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: usubo.i64
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; CHECK: subs x8, x0, x1
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; CHECK-NEXT: cset w0, lo
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%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: smulo.i32
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; CHECK: smull x8, w0, w1
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; CHECK-NEXT: lsr x9, x8, #32
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; CHECK-NEXT: cmp w9, w8, asr #31
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; CHECK-NEXT: cset w0, ne
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%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: smulo.i64
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; CHECK: mul x8, x0, x1
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; CHECK-NEXT: smulh x9, x0, x1
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; CHECK-NEXT: cmp x9, x8, asr #63
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; CHECK-NEXT: cset w0, ne
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%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: umulo.i32
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; CHECK: umull x8, w0, w1
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; CHECK-NEXT: cmp xzr, x8, lsr #32
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; CHECK-NEXT: cset w0, ne
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%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: umulo.i64
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; CHECK: umulh x8, x0, x1
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; CHECK-NEXT: cmp xzr, x8
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; CHECK-NEXT: cset w8, ne
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; CHECK-NEXT: mul x9, x0, x1
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%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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;
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; Check the use of the overflow bit in combination with a select instruction.
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;
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define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: saddo.select.i32
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; CHECK: cmn w0, w1
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; CHECK-NEXT: csel w0, w0, w1, vs
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: saddo.select.i64
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; CHECK: cmn x0, x1
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; CHECK-NEXT: csel x0, x0, x1, vs
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: uaddo.select.i32
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; CHECK: cmn w0, w1
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; CHECK-NEXT: csel w0, w0, w1, hs
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: uaddo.select.i64
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; CHECK: cmn x0, x1
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; CHECK-NEXT: csel x0, x0, x1, hs
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: ssubo.select.i32
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; CHECK: cmp w0, w1
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; CHECK-NEXT: csel w0, w0, w1, vs
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%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: ssubo.select.i64
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; CHECK: cmp x0, x1
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; CHECK-NEXT: csel x0, x0, x1, vs
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%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: usubo.select.i32
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; CHECK: cmp w0, w1
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; CHECK-NEXT: csel w0, w0, w1, lo
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: usubo.select.i64
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; CHECK: cmp x0, x1
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; CHECK-NEXT: csel x0, x0, x1, lo
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%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: smulo.select.i32
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; CHECK: smull x8, w0, w1
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; CHECK-NEXT: lsr x9, x8, #32
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; CHECK-NEXT: cmp w9, w8, asr #31
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; CHECK-NEXT: csel w0, w0, w1, ne
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%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: smulo.select.i64
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; CHECK: mul x8, x0, x1
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; CHECK-NEXT: smulh x9, x0, x1
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; CHECK-NEXT: cmp x9, x8, asr #63
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; CHECK-NEXT: csel x0, x0, x1, ne
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%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: umulo.select.i32
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; CHECK: umull x8, w0, w1
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; CHECK-NEXT: cmp xzr, x8, lsr #32
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; CHECK-NEXT: csel w0, w0, w1, ne
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%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: umulo.select.i64
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; CHECK: umulh x8, x0, x1
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; CHECK-NEXT: cmp xzr, x8
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; CHECK-NEXT: csel x0, x0, x1, ne
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%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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;
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; Check the use of the overflow bit in combination with a branch instruction.
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;
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define i1 @saddo.br.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: saddo.br.i32
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; CHECK: cmn w0, w1
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; CHECK-NEXT: b.vc
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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br i1 %obit, label %overflow, label %continue
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overflow:
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ret i1 false
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continue:
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ret i1 true
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}
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define i1 @saddo.br.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: saddo.br.i64
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; CHECK: cmn x0, x1
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; CHECK-NEXT: b.vc
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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br i1 %obit, label %overflow, label %continue
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overflow:
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ret i1 false
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continue:
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ret i1 true
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}
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define i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: uaddo.br.i32
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; CHECK: cmn w0, w1
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; CHECK-NEXT: b.lo
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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br i1 %obit, label %overflow, label %continue
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overflow:
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ret i1 false
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continue:
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ret i1 true
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}
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define i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: uaddo.br.i64
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; CHECK: cmn x0, x1
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; CHECK-NEXT: b.lo
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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br i1 %obit, label %overflow, label %continue
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overflow:
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ret i1 false
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continue:
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ret i1 true
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}
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define i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: ssubo.br.i32
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; CHECK: cmp w0, w1
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; CHECK-NEXT: b.vc
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%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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br i1 %obit, label %overflow, label %continue
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overflow:
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ret i1 false
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continue:
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ret i1 true
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}
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define i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: ssubo.br.i64
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; CHECK: cmp x0, x1
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; CHECK-NEXT: b.vc
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%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define i1 @usubo.br.i32(i32 %v1, i32 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: usubo.br.i32
|
|
; CHECK: cmp w0, w1
|
|
; CHECK-NEXT: b.hs
|
|
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define i1 @usubo.br.i64(i64 %v1, i64 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: usubo.br.i64
|
|
; CHECK: cmp x0, x1
|
|
; CHECK-NEXT: b.hs
|
|
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define i1 @smulo.br.i32(i32 %v1, i32 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: smulo.br.i32
|
|
; CHECK: smull x8, w0, w1
|
|
; CHECK-NEXT: lsr x9, x8, #32
|
|
; CHECK-NEXT: cmp w9, w8, asr #31
|
|
; CHECK-NEXT: b.eq
|
|
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define i1 @smulo.br.i64(i64 %v1, i64 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: smulo.br.i64
|
|
; CHECK: mul x8, x0, x1
|
|
; CHECK-NEXT: smulh x9, x0, x1
|
|
; CHECK-NEXT: cmp x9, x8, asr #63
|
|
; CHECK-NEXT: b.eq
|
|
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define i1 @umulo.br.i32(i32 %v1, i32 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: umulo.br.i32
|
|
; CHECK: umull x8, w0, w1
|
|
; CHECK-NEXT: cmp xzr, x8, lsr #32
|
|
; CHECK-NEXT: b.eq
|
|
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define i1 @umulo.br.i64(i64 %v1, i64 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: umulo.br.i64
|
|
; CHECK: umulh x8, x0, x1
|
|
; CHECK-NEXT: cbz
|
|
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
|
|
declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
|
|
declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
|
|
declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
|
|
declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
|
|
declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
|
|
|