mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-06 21:05:51 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
3.3 KiB
TableGen
96 lines
3.3 KiB
TableGen
//===- ARM64.td - Describe the ARM64 Target Machine --------*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target-independent interfaces which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ARM64 Subtarget features.
|
|
//
|
|
|
|
/// Cyclone has register move instructions which are "free".
|
|
def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
|
|
"Has zereo-cycle register moves">;
|
|
|
|
/// Cyclone has instructions which zero registers for "free".
|
|
def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
|
|
"Has zero-cycle zeroing instructions">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "ARM64RegisterInfo.td"
|
|
include "ARM64CallingConvention.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "ARM64Schedule.td"
|
|
include "ARM64InstrInfo.td"
|
|
|
|
def ARM64InstrInfo : InstrInfo;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ARM64 Processors supported.
|
|
//
|
|
include "ARM64SchedCyclone.td"
|
|
|
|
def : ProcessorModel<"arm64-generic", NoSchedModel, []>;
|
|
|
|
def : ProcessorModel<"cyclone", CycloneModel, [FeatureZCRegMove, FeatureZCZeroing]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly parser
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def GenericAsmParserVariant : AsmParserVariant {
|
|
int Variant = 0;
|
|
string Name = "generic";
|
|
}
|
|
|
|
def AppleAsmParserVariant : AsmParserVariant {
|
|
int Variant = 1;
|
|
string Name = "apple-neon";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly printer
|
|
//===----------------------------------------------------------------------===//
|
|
// ARM64 Uses the MC printer for asm output, so make sure the TableGen
|
|
// AsmWriter bits get associated with the correct class.
|
|
def GenericAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "InstPrinter";
|
|
int Variant = 0;
|
|
bit isMCAsmWriter = 1;
|
|
}
|
|
|
|
def AppleAsmWriter : AsmWriter {
|
|
let AsmWriterClassName = "AppleInstPrinter";
|
|
int Variant = 1;
|
|
int isMCAsmWriter = 1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target Declaration
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def ARM64 : Target {
|
|
let InstructionSet = ARM64InstrInfo;
|
|
let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
|
|
let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
|
|
}
|