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https://github.com/c64scene-ar/llvm-6502.git
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ed788b6283
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
2.3 KiB
LLVM
100 lines
2.3 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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define i32 @t1(i1 %c) nounwind readnone {
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entry:
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; ARM: t1
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; ARM: movw r{{[1-9]}}, #10
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; ARM: cmp r0, #0
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; ARM: moveq r{{[1-9]}}, #20
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; ARM: mov r0, r{{[1-9]}}
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; THUMB: t1
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; THUMB: movs r{{[1-9]}}, #10
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; THUMB: movt r{{[1-9]}}, #0
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; THUMB: cmp r0, #0
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; THUMB: it eq
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; THUMB: moveq r{{[1-9]}}, #20
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; THUMB: mov r0, r{{[1-9]}}
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%0 = select i1 %c, i32 10, i32 20
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ret i32 %0
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}
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define i32 @t2(i1 %c, i32 %a) nounwind readnone {
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entry:
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; ARM: t2
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; ARM: cmp r0, #0
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; ARM: moveq r{{[1-9]}}, #20
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; ARM: mov r0, r{{[1-9]}}
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; THUMB: t2
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; THUMB: cmp r0, #0
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; THUMB: it eq
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; THUMB: moveq r{{[1-9]}}, #20
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; THUMB: mov r0, r{{[1-9]}}
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%0 = select i1 %c, i32 %a, i32 20
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ret i32 %0
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}
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define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone {
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entry:
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; ARM: t3
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; ARM: cmp r0, #0
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; ARM: movne r{{[1-9]}}, r{{[1-9]}}
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; ARM: mov r0, r{{[1-9]}}
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; THUMB: t3
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; THUMB: cmp r0, #0
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; THUMB: it ne
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; THUMB: movne r{{[1-9]}}, r{{[1-9]}}
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; THUMB: mov r0, r{{[1-9]}}
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%0 = select i1 %c, i32 %a, i32 %b
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ret i32 %0
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}
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define i32 @t4(i1 %c) nounwind readnone {
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entry:
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; ARM: t4
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; ARM: mvn r{{[1-9]}}, #9
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; ARM: cmp r0, #0
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; ARM: mvneq r{{[1-9]}}, #0
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; ARM: mov r0, r{{[1-9]}}
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; THUMB: t4
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; THUMB: movw r{{[1-9]}}, #65526
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; THUMB: movt r{{[1-9]}}, #65535
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; THUMB: cmp r0, #0
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; THUMB: it eq
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; THUMB: mvneq r{{[1-9]}}, #0
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; THUMB: mov r0, r{{[1-9]}}
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%0 = select i1 %c, i32 -10, i32 -1
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ret i32 %0
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}
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define i32 @t5(i1 %c, i32 %a) nounwind readnone {
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entry:
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; ARM: t5
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; ARM: cmp r0, #0
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; ARM: mvneq r{{[1-9]}}, #1
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; ARM: mov r0, r{{[1-9]}}
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; THUMB: t5
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; THUMB: cmp r0, #0
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; THUMB: it eq
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; THUMB: mvneq r{{[1-9]}}, #1
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; THUMB: mov r0, r{{[1-9]}}
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%0 = select i1 %c, i32 %a, i32 -2
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ret i32 %0
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}
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; Check one large negative immediates.
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define i32 @t6(i1 %c, i32 %a) nounwind readnone {
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entry:
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; ARM: t6
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; ARM: cmp r0, #0
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; ARM: mvneq r{{[1-9]}}, #978944
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; ARM: mov r0, r{{[1-9]}}
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; THUMB: t6
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; THUMB: cmp r0, #0
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; THUMB: it eq
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; THUMB: mvneq r{{[1-9]}}, #978944
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; THUMB: mov r0, r{{[1-9]}}
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%0 = select i1 %c, i32 %a, i32 -978945
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ret i32 %0
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}
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