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AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An instruction might be using a register that can only be replaced with one from a subclass of getPhysicalRegisterRegClass. With this patch we use getMinimalPhysRegClass. This is correct, but conservative. We should check the uses of the register and select the largest register class that can be used in all of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108122 91177308-0d34-0410-b5e6-96231b3b80d8
771 lines
31 KiB
C++
771 lines
31 KiB
C++
//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes an abstract interface used to get information about a
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// target machines register file. This information is used for a variety of
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// purposed, especially register allocation.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETREGISTERINFO_H
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#define LLVM_TARGET_TARGETREGISTERINFO_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/ADT/DenseSet.h"
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#include <cassert>
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#include <functional>
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namespace llvm {
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class BitVector;
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class MachineFunction;
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class MachineMove;
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class RegScavenger;
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template<class T> class SmallVectorImpl;
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/// TargetRegisterDesc - This record contains all of the information known about
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/// a particular register. The AliasSet field (if not null) contains a pointer
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/// to a Zero terminated array of registers that this register aliases. This is
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/// needed for architectures like X86 which have AL alias AX alias EAX.
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/// Registers that this does not apply to simply should set this to null.
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/// The SubRegs field is a zero terminated array of registers that are
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/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
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/// The SuperRegs field is a zero terminated array of registers that are
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/// super-registers of the specific register, e.g. RAX, EAX, are super-registers
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/// of AX.
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///
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struct TargetRegisterDesc {
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const char *Name; // Printable name for the reg (for debugging)
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const unsigned *AliasSet; // Register Alias Set, described above
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const unsigned *SubRegs; // Sub-register set, described above
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const unsigned *SuperRegs; // Super-register set, described above
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};
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class TargetRegisterClass {
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public:
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typedef const unsigned* iterator;
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typedef const unsigned* const_iterator;
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typedef const EVT* vt_iterator;
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typedef const TargetRegisterClass* const * sc_iterator;
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private:
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unsigned ID;
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const char *Name;
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const vt_iterator VTs;
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const sc_iterator SubClasses;
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const sc_iterator SuperClasses;
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const sc_iterator SubRegClasses;
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const sc_iterator SuperRegClasses;
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const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
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const int CopyCost;
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const iterator RegsBegin, RegsEnd;
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DenseSet<unsigned> RegSet;
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public:
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TargetRegisterClass(unsigned id,
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const char *name,
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const EVT *vts,
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const TargetRegisterClass * const *subcs,
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const TargetRegisterClass * const *supcs,
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const TargetRegisterClass * const *subregcs,
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const TargetRegisterClass * const *superregcs,
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unsigned RS, unsigned Al, int CC,
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iterator RB, iterator RE)
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: ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
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SubRegClasses(subregcs), SuperRegClasses(superregcs),
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RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
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for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
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RegSet.insert(*I);
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}
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virtual ~TargetRegisterClass() {} // Allow subclasses
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/// getID() - Return the register class ID number.
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///
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unsigned getID() const { return ID; }
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/// getName() - Return the register class name for debugging.
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///
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const char *getName() const { return Name; }
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/// begin/end - Return all of the registers in this class.
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///
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iterator begin() const { return RegsBegin; }
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iterator end() const { return RegsEnd; }
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/// getNumRegs - Return the number of registers in this class.
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///
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unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
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/// getRegister - Return the specified register in the class.
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///
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unsigned getRegister(unsigned i) const {
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assert(i < getNumRegs() && "Register number out of range!");
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return RegsBegin[i];
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}
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/// contains - Return true if the specified register is included in this
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/// register class. This does not include virtual registers.
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bool contains(unsigned Reg) const {
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return RegSet.count(Reg);
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}
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/// contains - Return true if both registers are in this class.
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bool contains(unsigned Reg1, unsigned Reg2) const {
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return contains(Reg1) && contains(Reg2);
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}
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/// hasType - return true if this TargetRegisterClass has the ValueType vt.
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///
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bool hasType(EVT vt) const {
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for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i)
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if (VTs[i] == vt)
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return true;
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return false;
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}
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/// vt_begin / vt_end - Loop over all of the value types that can be
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/// represented by values in this register class.
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vt_iterator vt_begin() const {
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return VTs;
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}
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vt_iterator vt_end() const {
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vt_iterator I = VTs;
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while (I->getSimpleVT().SimpleTy != MVT::Other) ++I;
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return I;
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}
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/// subregclasses_begin / subregclasses_end - Loop over all of
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/// the subreg register classes of this register class.
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sc_iterator subregclasses_begin() const {
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return SubRegClasses;
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}
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sc_iterator subregclasses_end() const {
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sc_iterator I = SubRegClasses;
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while (*I != NULL) ++I;
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return I;
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}
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/// getSubRegisterRegClass - Return the register class of subregisters with
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/// index SubIdx, or NULL if no such class exists.
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const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
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assert(SubIdx>0 && "Invalid subregister index");
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return SubRegClasses[SubIdx-1];
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}
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/// superregclasses_begin / superregclasses_end - Loop over all of
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/// the superreg register classes of this register class.
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sc_iterator superregclasses_begin() const {
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return SuperRegClasses;
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}
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sc_iterator superregclasses_end() const {
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sc_iterator I = SuperRegClasses;
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while (*I != NULL) ++I;
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return I;
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}
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/// hasSubClass - return true if the specified TargetRegisterClass
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/// is a proper subset of this TargetRegisterClass.
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bool hasSubClass(const TargetRegisterClass *cs) const {
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for (int i = 0; SubClasses[i] != NULL; ++i)
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if (SubClasses[i] == cs)
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return true;
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return false;
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}
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/// subclasses_begin / subclasses_end - Loop over all of the classes
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/// that are proper subsets of this register class.
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sc_iterator subclasses_begin() const {
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return SubClasses;
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}
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sc_iterator subclasses_end() const {
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sc_iterator I = SubClasses;
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while (*I != NULL) ++I;
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return I;
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}
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/// hasSuperClass - return true if the specified TargetRegisterClass is a
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/// proper superset of this TargetRegisterClass.
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bool hasSuperClass(const TargetRegisterClass *cs) const {
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for (int i = 0; SuperClasses[i] != NULL; ++i)
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if (SuperClasses[i] == cs)
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return true;
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return false;
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}
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/// superclasses_begin / superclasses_end - Loop over all of the classes
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/// that are proper supersets of this register class.
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sc_iterator superclasses_begin() const {
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return SuperClasses;
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}
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sc_iterator superclasses_end() const {
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sc_iterator I = SuperClasses;
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while (*I != NULL) ++I;
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return I;
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}
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/// isASubClass - return true if this TargetRegisterClass is a subset
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/// class of at least one other TargetRegisterClass.
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bool isASubClass() const {
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return SuperClasses[0] != 0;
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}
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/// allocation_order_begin/end - These methods define a range of registers
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/// which specify the registers in this class that are valid to register
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/// allocate, and the preferred order to allocate them in. For example,
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/// callee saved registers should be at the end of the list, because it is
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/// cheaper to allocate caller saved registers.
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///
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/// These methods take a MachineFunction argument, which can be used to tune
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/// the allocatable registers based on the characteristics of the function.
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/// One simple example is that the frame pointer register can be used if
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/// frame-pointer-elimination is performed.
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///
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/// By default, these methods return all registers in the class.
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///
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virtual iterator allocation_order_begin(const MachineFunction &MF) const {
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return begin();
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}
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virtual iterator allocation_order_end(const MachineFunction &MF) const {
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return end();
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}
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/// getSize - Return the size of the register in bytes, which is also the size
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/// of a stack slot allocated to hold a spilled copy of this register.
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unsigned getSize() const { return RegSize; }
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/// getAlignment - Return the minimum required alignment for a register of
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/// this class.
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unsigned getAlignment() const { return Alignment; }
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/// getCopyCost - Return the cost of copying a value between two registers in
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/// this class. A negative number means the register class is very expensive
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/// to copy e.g. status flag register classes.
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int getCopyCost() const { return CopyCost; }
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};
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/// TargetRegisterInfo base class - We assume that the target defines a static
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/// array of TargetRegisterDesc objects that represent all of the machine
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/// registers that the target has. As such, we simply have to track a pointer
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/// to this array so that we can turn register number into a register
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/// descriptor.
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///
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class TargetRegisterInfo {
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protected:
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const unsigned* SubregHash;
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const unsigned SubregHashSize;
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const unsigned* AliasesHash;
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const unsigned AliasesHashSize;
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public:
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typedef const TargetRegisterClass * const * regclass_iterator;
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private:
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const TargetRegisterDesc *Desc; // Pointer to the descriptor array
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const char *const *SubRegIndexNames; // Names of subreg indexes.
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unsigned NumRegs; // Number of entries in the array
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regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
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int CallFrameSetupOpcode, CallFrameDestroyOpcode;
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protected:
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TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
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regclass_iterator RegClassBegin,
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regclass_iterator RegClassEnd,
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const char *const *subregindexnames,
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int CallFrameSetupOpcode = -1,
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int CallFrameDestroyOpcode = -1,
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const unsigned* subregs = 0,
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const unsigned subregsize = 0,
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const unsigned* aliases = 0,
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const unsigned aliasessize = 0);
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virtual ~TargetRegisterInfo();
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public:
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enum { // Define some target independent constants
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/// NoRegister - This physical register is not a real target register. It
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/// is useful as a sentinal.
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NoRegister = 0,
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/// FirstVirtualRegister - This is the first register number that is
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/// considered to be a 'virtual' register, which is part of the SSA
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/// namespace. This must be the same for all targets, which means that each
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/// target is limited to this fixed number of registers.
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FirstVirtualRegister = 1024
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};
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/// isPhysicalRegister - Return true if the specified register number is in
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/// the physical register namespace.
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static bool isPhysicalRegister(unsigned Reg) {
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assert(Reg && "this is not a register!");
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return Reg < FirstVirtualRegister;
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}
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/// isVirtualRegister - Return true if the specified register number is in
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/// the virtual register namespace.
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static bool isVirtualRegister(unsigned Reg) {
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assert(Reg && "this is not a register!");
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return Reg >= FirstVirtualRegister;
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}
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/// getMinimalPhysRegClass - Returns the Register Class of a physical
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/// register of the given type, picking the most sub register class of
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/// the right type that contains this physreg.
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const TargetRegisterClass *
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getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
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/// getAllocatableSet - Returns a bitset indexed by register number
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/// indicating if a register is allocatable or not. If a register class is
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/// specified, returns the subset for the class.
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BitVector getAllocatableSet(const MachineFunction &MF,
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const TargetRegisterClass *RC = NULL) const;
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const TargetRegisterDesc &operator[](unsigned RegNo) const {
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assert(RegNo < NumRegs &&
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"Attempting to access record for invalid register number!");
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return Desc[RegNo];
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}
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/// Provide a get method, equivalent to [], but more useful if we have a
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/// pointer to this object.
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///
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const TargetRegisterDesc &get(unsigned RegNo) const {
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return operator[](RegNo);
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}
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/// getAliasSet - Return the set of registers aliased by the specified
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/// register, or a null list of there are none. The list returned is zero
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/// terminated.
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///
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const unsigned *getAliasSet(unsigned RegNo) const {
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return get(RegNo).AliasSet;
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}
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/// getSubRegisters - Return the list of registers that are sub-registers of
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/// the specified register, or a null list of there are none. The list
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/// returned is zero terminated and sorted according to super-sub register
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/// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
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///
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const unsigned *getSubRegisters(unsigned RegNo) const {
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return get(RegNo).SubRegs;
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}
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/// getSuperRegisters - Return the list of registers that are super-registers
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/// of the specified register, or a null list of there are none. The list
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/// returned is zero terminated and sorted according to super-sub register
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/// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
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///
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const unsigned *getSuperRegisters(unsigned RegNo) const {
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return get(RegNo).SuperRegs;
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}
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/// getName - Return the human-readable symbolic target-specific name for the
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/// specified physical register.
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const char *getName(unsigned RegNo) const {
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return get(RegNo).Name;
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}
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/// getNumRegs - Return the number of registers this target has (useful for
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/// sizing arrays holding per register information)
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unsigned getNumRegs() const {
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return NumRegs;
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}
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/// getSubRegIndexName - Return the human-readable symbolic target-specific
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/// name for the specified SubRegIndex.
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const char *getSubRegIndexName(unsigned SubIdx) const {
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assert(SubIdx && "This is not a subregister index");
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return SubRegIndexNames[SubIdx-1];
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}
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/// regsOverlap - Returns true if the two registers are equal or alias each
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/// other. The registers may be virtual register.
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bool regsOverlap(unsigned regA, unsigned regB) const {
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if (regA == regB)
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return true;
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if (isVirtualRegister(regA) || isVirtualRegister(regB))
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return false;
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// regA and regB are distinct physical registers. Do they alias?
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size_t index = (regA + regB * 37) & (AliasesHashSize-1);
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unsigned ProbeAmt = 0;
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while (AliasesHash[index*2] != 0 &&
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AliasesHash[index*2+1] != 0) {
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if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
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return true;
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index = (index + ProbeAmt) & (AliasesHashSize-1);
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ProbeAmt += 2;
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}
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return false;
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}
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/// isSubRegister - Returns true if regB is a sub-register of regA.
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///
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bool isSubRegister(unsigned regA, unsigned regB) const {
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// SubregHash is a simple quadratically probed hash table.
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size_t index = (regA + regB * 37) & (SubregHashSize-1);
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unsigned ProbeAmt = 2;
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while (SubregHash[index*2] != 0 &&
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SubregHash[index*2+1] != 0) {
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if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
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return true;
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index = (index + ProbeAmt) & (SubregHashSize-1);
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ProbeAmt += 2;
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}
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return false;
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}
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/// isSuperRegister - Returns true if regB is a super-register of regA.
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///
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bool isSuperRegister(unsigned regA, unsigned regB) const {
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return isSubRegister(regB, regA);
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}
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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/// callee saved registers on this target. The register should be in the
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/// order of desired callee-save stack frame offset. The first register is
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/// closed to the incoming stack pointer if stack grows down, and vice versa.
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virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
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const = 0;
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses
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/// and should be considered unavailable at all times, e.g. SP, RA. This is
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/// used by register scavenger to determine what registers are free.
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virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
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/// getSubReg - Returns the physical register number of sub-register "Index"
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/// for physical register RegNo. Return zero if the sub-register does not
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/// exist.
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virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
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/// getSubRegIndex - For a given register pair, return the sub-register index
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/// if the second register is a sub-register of the first. Return zero
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/// otherwise.
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virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
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/// getMatchingSuperReg - Return a super-register of the specified register
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/// Reg so its sub-register of index SubIdx is Reg.
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unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
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const TargetRegisterClass *RC) const {
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for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
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if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
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return SR;
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return 0;
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}
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/// canCombineSubRegIndices - Given a register class and a list of
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/// subregister indices, return true if it's possible to combine the
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/// subregister indices into one that corresponds to a larger
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/// subregister. Return the new subregister index by reference. Note the
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/// new index may be zero if the given subregisters can be combined to
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/// form the whole register.
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virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
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SmallVectorImpl<unsigned> &SubIndices,
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unsigned &NewSubIdx) const {
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return 0;
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}
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/// getMatchingSuperRegClass - Return a subclass of the specified register
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/// class A so that each register in it has a sub-register of the
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/// specified sub-register index which is in the specified register class B.
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virtual const TargetRegisterClass *
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getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B, unsigned Idx) const {
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return 0;
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}
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/// composeSubRegIndices - Return the subregister index you get from composing
|
|
/// two subregister indices.
|
|
///
|
|
/// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
|
|
/// returns c. Note that composeSubRegIndices does not tell you about illegal
|
|
/// compositions. If R does not have a subreg a, or R:a does not have a subreg
|
|
/// b, composeSubRegIndices doesn't tell you.
|
|
///
|
|
/// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
|
|
/// ssub_0:S0 - ssub_3:S3 subregs.
|
|
/// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
|
|
///
|
|
virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
|
|
// This default implementation is correct for most targets.
|
|
return b;
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Register Class Information
|
|
//
|
|
|
|
/// Register class iterators
|
|
///
|
|
regclass_iterator regclass_begin() const { return RegClassBegin; }
|
|
regclass_iterator regclass_end() const { return RegClassEnd; }
|
|
|
|
unsigned getNumRegClasses() const {
|
|
return (unsigned)(regclass_end()-regclass_begin());
|
|
}
|
|
|
|
/// getRegClass - Returns the register class associated with the enumeration
|
|
/// value. See class TargetOperandInfo.
|
|
const TargetRegisterClass *getRegClass(unsigned i) const {
|
|
assert(i < getNumRegClasses() && "Register Class ID out of range");
|
|
return RegClassBegin[i];
|
|
}
|
|
|
|
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
|
|
/// values. If a target supports multiple different pointer register classes,
|
|
/// kind specifies which one is indicated.
|
|
virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
|
|
assert(0 && "Target didn't implement getPointerRegClass!");
|
|
return 0; // Must return a value in order to compile with VS 2005
|
|
}
|
|
|
|
/// getCrossCopyRegClass - Returns a legal register class to copy a register
|
|
/// in the specified class to or from. Returns NULL if it is possible to copy
|
|
/// between a two registers of the specified class.
|
|
virtual const TargetRegisterClass *
|
|
getCrossCopyRegClass(const TargetRegisterClass *RC) const {
|
|
return NULL;
|
|
}
|
|
|
|
/// getAllocationOrder - Returns the register allocation order for a specified
|
|
/// register class in the form of a pair of TargetRegisterClass iterators.
|
|
virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
|
|
getAllocationOrder(const TargetRegisterClass *RC,
|
|
unsigned HintType, unsigned HintReg,
|
|
const MachineFunction &MF) const {
|
|
return std::make_pair(RC->allocation_order_begin(MF),
|
|
RC->allocation_order_end(MF));
|
|
}
|
|
|
|
/// ResolveRegAllocHint - Resolves the specified register allocation hint
|
|
/// to a physical register. Returns the physical register if it is successful.
|
|
virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
|
|
const MachineFunction &MF) const {
|
|
if (Type == 0 && Reg && isPhysicalRegister(Reg))
|
|
return Reg;
|
|
return 0;
|
|
}
|
|
|
|
/// UpdateRegAllocHint - A callback to allow target a chance to update
|
|
/// register allocation hints when a register is "changed" (e.g. coalesced)
|
|
/// to another register. e.g. On ARM, some virtual registers should target
|
|
/// register pairs, if one of pair is coalesced to another register, the
|
|
/// allocation hint of the other half of the pair should be changed to point
|
|
/// to the new register.
|
|
virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
|
|
MachineFunction &MF) const {
|
|
// Do nothing.
|
|
}
|
|
|
|
/// targetHandlesStackFrameRounding - Returns true if the target is
|
|
/// responsible for rounding up the stack frame (probably at emitPrologue
|
|
/// time).
|
|
virtual bool targetHandlesStackFrameRounding() const {
|
|
return false;
|
|
}
|
|
|
|
/// requiresRegisterScavenging - returns true if the target requires (and can
|
|
/// make use of) the register scavenger.
|
|
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
|
|
return false;
|
|
}
|
|
|
|
/// requiresFrameIndexScavenging - returns true if the target requires post
|
|
/// PEI scavenging of registers for materializing frame index constants.
|
|
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
|
|
return false;
|
|
}
|
|
|
|
/// hasFP - Return true if the specified function should have a dedicated
|
|
/// frame pointer register. For most targets this is true only if the function
|
|
/// has variable sized allocas or if frame pointer elimination is disabled.
|
|
virtual bool hasFP(const MachineFunction &MF) const = 0;
|
|
|
|
/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
|
|
/// not required, we reserve argument space for call sites in the function
|
|
/// immediately on entry to the current function. This eliminates the need for
|
|
/// add/sub sp brackets around call sites. Returns true if the call frame is
|
|
/// included as part of the stack frame.
|
|
virtual bool hasReservedCallFrame(MachineFunction &MF) const {
|
|
return !hasFP(MF);
|
|
}
|
|
|
|
/// canSimplifyCallFramePseudos - When possible, it's best to simplify the
|
|
/// call frame pseudo ops before doing frame index elimination. This is
|
|
/// possible only when frame index references between the pseudos won't
|
|
/// need adjusted for the call frame adjustments. Normally, that's true
|
|
/// if the function has a reserved call frame or a frame pointer. Some
|
|
/// targets (Thumb2, for example) may have more complicated criteria,
|
|
/// however, and can override this behavior.
|
|
virtual bool canSimplifyCallFramePseudos(MachineFunction &MF) const {
|
|
return hasReservedCallFrame(MF) || hasFP(MF);
|
|
}
|
|
|
|
/// hasReservedSpillSlot - Return true if target has reserved a spill slot in
|
|
/// the stack frame of the given function for the specified register. e.g. On
|
|
/// x86, if the frame register is required, the first fixed stack object is
|
|
/// reserved as its spill slot. This tells PEI not to create a new stack frame
|
|
/// object for the given register. It should be called only after
|
|
/// processFunctionBeforeCalleeSavedScan().
|
|
virtual bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
|
|
int &FrameIdx) const {
|
|
return false;
|
|
}
|
|
|
|
/// needsStackRealignment - true if storage within the function requires the
|
|
/// stack pointer to be aligned more than the normal calling convention calls
|
|
/// for.
|
|
virtual bool needsStackRealignment(const MachineFunction &MF) const {
|
|
return false;
|
|
}
|
|
|
|
/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
|
|
/// frame setup/destroy instructions if they exist (-1 otherwise). Some
|
|
/// targets use pseudo instructions in order to abstract away the difference
|
|
/// between operating with a frame pointer and operating without, through the
|
|
/// use of these two instructions.
|
|
///
|
|
int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
|
|
int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
|
|
|
|
/// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
|
|
/// code insertion to eliminate call frame setup and destroy pseudo
|
|
/// instructions (but only if the Target is using them). It is responsible
|
|
/// for eliminating these instructions, replacing them with concrete
|
|
/// instructions. This method need only be implemented if using call frame
|
|
/// setup/destroy pseudo instructions.
|
|
///
|
|
virtual void
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const {
|
|
assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
|
|
"eliminateCallFramePseudoInstr must be implemented if using"
|
|
" call frame setup/destroy pseudo instructions!");
|
|
assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
|
|
}
|
|
|
|
/// processFunctionBeforeCalleeSavedScan - This method is called immediately
|
|
/// before PrologEpilogInserter scans the physical registers used to determine
|
|
/// what callee saved registers should be spilled. This method is optional.
|
|
virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
RegScavenger *RS = NULL) const {
|
|
|
|
}
|
|
|
|
/// processFunctionBeforeFrameFinalized - This method is called immediately
|
|
/// before the specified functions frame layout (MF.getFrameInfo()) is
|
|
/// finalized. Once the frame is finalized, MO_FrameIndex operands are
|
|
/// replaced with direct constants. This method is optional.
|
|
///
|
|
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
|
|
}
|
|
|
|
/// saveScavengerRegister - Spill the register so it can be used by the
|
|
/// register scavenger. Return true if the register was spilled, false
|
|
/// otherwise. If this function does not spill the register, the scavenger
|
|
/// will instead spill it to the emergency spill slot.
|
|
///
|
|
virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
MachineBasicBlock::iterator &UseMI,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Reg) const {
|
|
return false;
|
|
}
|
|
|
|
/// eliminateFrameIndex - This method must be overriden to eliminate abstract
|
|
/// frame indices from instructions which may use them. The instruction
|
|
/// referenced by the iterator contains an MO_FrameIndex operand which must be
|
|
/// eliminated by this method. This method may modify or replace the
|
|
/// specified instruction, as long as it keeps the iterator pointing at the
|
|
/// finished product. SPAdj is the SP adjustment due to call frame setup
|
|
/// instruction.
|
|
///
|
|
/// When -enable-frame-index-scavenging is enabled, the virtual register
|
|
/// allocated for this frame index is returned and its value is stored in
|
|
/// *Value.
|
|
typedef std::pair<unsigned, int> FrameIndexValue;
|
|
virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
|
int SPAdj, FrameIndexValue *Value = NULL,
|
|
RegScavenger *RS=NULL) const = 0;
|
|
|
|
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
|
|
/// the function.
|
|
virtual void emitPrologue(MachineFunction &MF) const = 0;
|
|
virtual void emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const = 0;
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
/// Debug information queries.
|
|
|
|
/// getDwarfRegNum - Map a target register to an equivalent dwarf register
|
|
/// number. Returns -1 if there is no equivalent value. The second
|
|
/// parameter allows targets to use different numberings for EH info and
|
|
/// debugging info.
|
|
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
|
|
|
|
/// getFrameRegister - This method should return the register used as a base
|
|
/// for values allocated in the current stack frame.
|
|
virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
|
|
|
|
/// getFrameIndexOffset - Returns the displacement from the frame register to
|
|
/// the stack frame of the specified index.
|
|
virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
|
|
|
|
/// getFrameIndexReference - This method should return the base register
|
|
/// and offset used to reference a frame index location. The offset is
|
|
/// returned directly, and the base register is returned via FrameReg.
|
|
virtual int getFrameIndexReference(const MachineFunction &MF, int FI,
|
|
unsigned &FrameReg) const {
|
|
// By default, assume all frame indices are referenced via whatever
|
|
// getFrameRegister() says. The target can override this if it's doing
|
|
// something different.
|
|
FrameReg = getFrameRegister(MF);
|
|
return getFrameIndexOffset(MF, FI);
|
|
}
|
|
|
|
/// getRARegister - This method should return the register where the return
|
|
/// address can be found.
|
|
virtual unsigned getRARegister() const = 0;
|
|
|
|
/// getInitialFrameState - Returns a list of machine moves that are assumed
|
|
/// on entry to all functions. Note that LabelID is ignored (assumed to be
|
|
/// the beginning of the function.)
|
|
virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
|
|
};
|
|
|
|
|
|
// This is useful when building IndexedMaps keyed on virtual registers
|
|
struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
|
|
unsigned operator()(unsigned Reg) const {
|
|
return Reg - TargetRegisterInfo::FirstVirtualRegister;
|
|
}
|
|
};
|
|
|
|
/// getCommonSubClass - find the largest common subclass of A and B. Return NULL
|
|
/// if there is no common subclass.
|
|
const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
|
|
const TargetRegisterClass *B);
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|