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86245071b5
Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
62 lines
2.6 KiB
C++
62 lines
2.6 KiB
C++
//===-- AMDGPUInstPrinter.h - AMDGPU MC Inst -> ASM interface ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPUINSTPRINTER_H
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#define AMDGPUINSTPRINTER_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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class AMDGPUInstPrinter : public MCInstPrinter {
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public:
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AMDGPUInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI)
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: MCInstPrinter(MAI, MII, MRI) {}
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//Autogenerated by tblgen
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void printInstruction(const MCInst *MI, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
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private:
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void printRegOperand(unsigned RegNo, raw_ostream &O);
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
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StringRef Asm, StringRef Default = "");
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void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printOMOD(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printRel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printUpdateExecMask(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printUpdatePred(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printBankSwizzle(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printWaitFlag(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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};
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} // End namespace llvm
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#endif // AMDGPUINSTRPRINTER_H
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