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There were some that might even matter in X86FastISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64437 91177308-0d34-0410-b5e6-96231b3b80d8
140 lines
5.2 KiB
C++
140 lines
5.2 KiB
C++
//===-- X86FloatingPoint.cpp - FP_REG_KILL inserter -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the pass which inserts FP_REG_KILL instructions.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "x86-codegen"
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/Instructions.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumFPKill, "Number of FP_REG_KILL instructions added");
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namespace {
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struct VISIBILITY_HIDDEN FPRegKiller : public MachineFunctionPass {
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static char ID;
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FPRegKiller() : MachineFunctionPass(&ID) {}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const { return "X86 FP_REG_KILL inserter"; }
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};
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char FPRegKiller::ID = 0;
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}
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FunctionPass *llvm::createX87FPRegKillInserterPass() { return new FPRegKiller(); }
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bool FPRegKiller::runOnMachineFunction(MachineFunction &MF) {
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// If we are emitting FP stack code, scan the basic block to determine if this
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// block defines any FP values. If so, put an FP_REG_KILL instruction before
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// the terminator of the block.
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// Note that FP stack instructions are used in all modes for long double,
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// so we always need to do this check.
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// Also note that it's possible for an FP stack register to be live across
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// an instruction that produces multiple basic blocks (SSE CMOV) so we
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// must check all the generated basic blocks.
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// Scan all of the machine instructions in these MBBs, checking for FP
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// stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
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// Fast-path: If nothing is using the x87 registers, we don't need to do
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// any scanning.
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MachineRegisterInfo &MRI = MF.getRegInfo();
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if (MRI.getRegClassVirtRegs(X86::RFP80RegisterClass).empty() &&
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MRI.getRegClassVirtRegs(X86::RFP64RegisterClass).empty() &&
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MRI.getRegClassVirtRegs(X86::RFP32RegisterClass).empty())
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return false;
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bool Changed = false;
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const X86Subtarget &Subtarget = MF.getTarget().getSubtarget<X86Subtarget>();
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MachineFunction::iterator MBBI = MF.begin();
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MachineFunction::iterator EndMBB = MF.end();
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for (; MBBI != EndMBB; ++MBBI) {
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MachineBasicBlock *MBB = MBBI;
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// If this block returns, ignore it. We don't want to insert an FP_REG_KILL
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// before the return.
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if (!MBB->empty()) {
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MachineBasicBlock::iterator EndI = MBB->end();
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--EndI;
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if (EndI->getDesc().isReturn())
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continue;
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}
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bool ContainsFPCode = false;
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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!ContainsFPCode && I != E; ++I) {
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if (I->getNumOperands() != 0 && I->getOperand(0).isReg()) {
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const TargetRegisterClass *clas;
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for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
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if (I->getOperand(op).isReg() && I->getOperand(op).isDef() &&
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TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
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((clas = MRI.getRegClass(I->getOperand(op).getReg())) ==
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X86::RFP32RegisterClass ||
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clas == X86::RFP64RegisterClass ||
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clas == X86::RFP80RegisterClass)) {
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ContainsFPCode = true;
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break;
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}
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}
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}
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}
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// Check PHI nodes in successor blocks. These PHI's will be lowered to have
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// a copy of the input value in this block. In SSE mode, we only care about
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// 80-bit values.
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if (!ContainsFPCode) {
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// Final check, check LLVM BB's that are successors to the LLVM BB
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// corresponding to BB for FP PHI nodes.
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const BasicBlock *LLVMBB = MBB->getBasicBlock();
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const PHINode *PN;
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for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
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!ContainsFPCode && SI != E; ++SI) {
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for (BasicBlock::const_iterator II = SI->begin();
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(PN = dyn_cast<PHINode>(II)); ++II) {
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if (PN->getType()==Type::X86_FP80Ty ||
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(!Subtarget.hasSSE1() && PN->getType()->isFloatingPoint()) ||
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(!Subtarget.hasSSE2() && PN->getType()==Type::DoubleTy)) {
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ContainsFPCode = true;
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break;
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}
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}
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}
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}
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// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
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if (ContainsFPCode) {
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BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc::getUnknownLoc(),
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MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL));
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++NumFPKill;
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Changed = true;
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}
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}
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return Changed;
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}
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