Rafael Espindola 688e7b3049 This reverts commit r239529 and r239514. ... Revert "[AArch64] Match interleaved memory accesses into ldN/stN instructions." Revert "Fixing MSVC 2013 build error." The test/CodeGen/AArch64/aarch64-interleaved-accesses.ll test was failing on OS X. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239544 91177308-0d34-0410-b5e6-96231b3b80d8		2015-06-11 17:30:33 +00:00
..
AArch64	This reverts commit r239529 and r239514.	2015-06-11 17:30:33 +00:00
ARM	Add explicit -mtriple=arm-unknown to llvm/test/CodeGen/ARM/disable-tail-calls.ll, to satisfy *-win32.	2015-06-09 23:33:25 +00:00
BPF	[bpf] rename triple names bpf_be -> bpfeb	2015-06-05 16:11:14 +00:00
CPP
Generic	Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).	2015-05-27 18:02:19 +00:00
Hexagon	[Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.	2015-06-10 16:52:32 +00:00
Inputs
Mips	[mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.	2015-06-02 20:32:50 +00:00
MIR	MIR Serialization: use correct line and column numbers for LLVM IR errors.	2015-05-29 17:05:41 +00:00
MSP430
NVPTX	[NVPTX] fix a crash bug in NVPTXFavorNonGenericAddrSpaces	2015-06-09 21:50:32 +00:00
PowerPC	LLVM support for vector quad bit permute and gather instructions through builtins	2015-06-11 06:21:25 +00:00
R600	Revert "Fix merges of non-zero vector stores"	2015-06-11 17:25:24 +00:00
SPARC
SystemZ
Thumb	Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM."	2015-06-05 18:01:28 +00:00
Thumb2	ARM: Thumb2 LDRD/STRD supports independent input/output regs	2015-06-03 16:30:24 +00:00
WinEH
X86	Revert "Fix merges of non-zero vector stores"	2015-06-11 17:25:24 +00:00
XCore