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https://github.com/c64scene-ar/llvm-6502.git
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b3fa233048
Summary: Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly position llvm-mc's fixup placeholders for big-endian. See PR19836 for full details of the issue. To summarize, the fixup placeholders do not account for endianness properly and the implementations of getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset from different ends of the instruction encoding to compensate. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3889 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209514 91177308-0d34-0410-b5e6-96231b3b80d8
84 lines
2.5 KiB
ArmAsm
84 lines
2.5 KiB
ArmAsm
# RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mips-unknown-unknown %s | FileCheck %s
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#
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# CHECK: .text
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# CHECK: $BB0_2:
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# CHECK: .abicalls
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$BB0_2:
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.ent directives_test
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.abicalls
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.frame $sp,0,$ra
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.mask 0x00000000,0
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.fmask 0x00000000,0
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# CHECK: .set noreorder
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# CHECK: b 1332 # encoding: [0x10,0x00,0x01,0x4d]
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# CHECK-NOT: nop
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# CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
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# CHECK-NOT: nop
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# CHECK: jal 1328 # encoding: [0x0c,0x00,0x01,0x4c]
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# CHECK-NOT: nop
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.set noreorder
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b 1332
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j 1328
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jal 1328
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.set nomacro
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.set noat
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$JTI0_0:
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.gpword ($BB0_2)
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.word 0x77fffffc
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# CHECK: $JTI0_0:
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# CHECK: .gpword ($BB0_2)
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# CHECK: .4byte 2013265916
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.set at=$12
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.set macro
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# CHECK: .set reorder
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# CHECK: b 1332 # encoding: [0x10,0x00,0x01,0x4d]
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK: jal 1328 # encoding: [0x0c,0x00,0x01,0x4c]
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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.set reorder
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$BB0_4:
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b 1332
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j 1328
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jal 1328
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.set at=$a0
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.set STORE_MASK,$t7
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.set FPU_MASK,$f7
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.set $tmp7, $BB0_4-$BB0_2
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.set f6,$f6
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# CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85]
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# CHECK: lui $1, %hi($tmp7) # encoding: [0x3c,0x01,A,A]
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# CHECK: # fixup A - offset: 0, value: ($tmp7)@ABS_HI, kind: fixup_Mips_HI16
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abs.s f6,FPU_MASK
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lui $1, %hi($tmp7)
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# CHECK: .set mips32r2
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# CHECK: ldxc1 $f0, $zero($5) # encoding: [0x4c,0xa0,0x00,0x01]
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# CHECK: luxc1 $f0, $6($5) # encoding: [0x4c,0xa6,0x00,0x05]
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# CHECK: lwxc1 $f6, $2($5) # encoding: [0x4c,0xa2,0x01,0x80]
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.set mips32r2
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ldxc1 $f0, $zero($5)
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luxc1 $f0, $6($5)
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lwxc1 $f6, $2($5)
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# CHECK: .set mips64
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# CHECK: dadd $3, $3, $3
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.set mips64
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dadd $3, $3, $3 # encoding: [0x00,0x62,0x18,0x2c]
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# CHECK: .set mips64r2
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# CHECK: drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba]
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.set mips64r2
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drotr $9, $6, 30
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# CHECK: .set dsp
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# CHECK: lbux $7, $10($11) # encoding: [0x7d,0x6a,0x39,0x8a]
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# CHECK: lhx $5, $6($7) # encoding: [0x7c,0xe6,0x29,0x0a]
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.set dsp
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lbux $7, $10($11)
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lhx $5, $6($7)
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