Jim Grosbach fd03ccdded ARM don't use MCRelaxAll, as it's not safe on ARM. ... The ARM code generator makes aggressive assumptions about the encodings being selected for branches which MCRelaxAll invalidates. rdar://11006355 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152268 91177308-0d34-0410-b5e6-96231b3b80d8		2012-03-08 00:07:52 +00:00
..
ARMAddressingModes.h	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
ARMAsmBackend.cpp	ARM BL/BLX instruction fixups should use relocations.	2012-02-27 21:36:23 +00:00
ARMBaseInfo.h	ARM more NEON VLD/VST composite physical register refactoring.	2012-03-06 23:10:38 +00:00
ARMELFObjectWriter.cpp	ARM BL/BLX instruction fixups should use relocations.	2012-02-27 21:36:23 +00:00
ARMFixupKinds.h	ARM BL/BLX instruction fixups should use relocations.	2012-02-27 21:36:23 +00:00
ARMMachObjectWriter.cpp	ARM BL/BLX instruction fixups should use relocations.	2012-02-27 21:36:23 +00:00
ARMMCAsmInfo.cpp	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
ARMMCAsmInfo.h	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
ARMMCCodeEmitter.cpp	ARM BL/BLX instruction fixups should use relocations.	2012-02-27 21:36:23 +00:00
ARMMCExpr.cpp	Convert assert(0) to llvm_unreachable	2012-02-07 02:50:20 +00:00
ARMMCExpr.h	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
ARMMCTargetDesc.cpp	ARM don't use MCRelaxAll, as it's not safe on ARM.	2012-03-08 00:07:52 +00:00
ARMMCTargetDesc.h	Move the ARM specific parts of the ELF writer to Target/ARM.	2011-12-22 00:37:50 +00:00
CMakeLists.txt	Hopefully fix the cmake build.	2011-12-22 01:11:01 +00:00
LLVMBuild.txt	LLVMBuild: Remove trailing newline, which irked me.	2011-12-12 19:48:00 +00:00
Makefile