Daniel Sanders a39d3ab819 [mips][mips64r6] Correct the encoding of dmuh, dmuhu, dmul, and dmulu. ... We have detected a documentation bug in the encoding tables of the released MIPS64r6 specification that has resulted in the wrong encodings being used for these instructions in LLVM. This commit corrects them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212330 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-04 10:08:27 +00:00
..
AArch64	Condition codes AL and NV are invalid in the aliases that use	2014-06-10 13:11:35 +00:00
ARM	ARM: honor hex immediate formatting for ldr/str i12 offsets.	2014-06-11 20:26:45 +00:00
Mips	[mips][mips64r6] Correct the encoding of dmuh, dmuhu, dmul, and dmulu.	2014-07-04 10:08:27 +00:00
PowerPC
Sparc
SystemZ
X86	[Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields	2014-06-24 01:42:32 +00:00
XCore