Matthias Braun 5b17297b3d [CodeGen] Add print and verify pass after each MachineFunctionPass by default ... Previously print+verify passes were added in a very unsystematic way, which is annoying when debugging as you miss intermediate steps and allows bugs to stay unnotice when no verification is performed. To make this change practical I added the possibility to explicitely disable verification. I used this option on all places where no verification was performed previously (because alot of places actually don't pass the MachineVerifier). In the long term these problems should be fixed properly and verification enabled after each pass. I'll enable some more verification in subsequent commits. This is the 2nd attempt at this after realizing that PassManager::add() may actually delete the pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224059 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-11 21:26:47 +00:00
..
AsmParser
InstPrinter
MCTargetDesc	R600/SI: Restore PrivateGlobalPrefix to the default ELF value of ".L"	2014-12-06 05:34:34 +00:00
TargetInfo
AMDGPU.h
AMDGPU.td	R600/SI: Add VI instructions	2014-12-07 12:18:57 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPUAsmPrinter.cpp	Silencing a 32-bit implicit conversion warning in MSVC; NFC.	2014-12-03 14:39:58 +00:00
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp	R600/SI: Add VI instructions	2014-12-07 12:18:57 +00:00
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td
AMDGPUInstructions.td
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp
AMDGPUISelLowering.cpp	R600/SI: Update instruction conversions for VI	2014-12-07 12:19:03 +00:00
AMDGPUISelLowering.h
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp	R600/SI: Add VI instructions	2014-12-07 12:18:57 +00:00
AMDGPUMCInstLower.h	R600/SI: Add VI instructions	2014-12-07 12:18:57 +00:00
AMDGPUPromoteAlloca.cpp
AMDGPURegisterInfo.cpp	R600/SI: Enable inline assembly	2014-12-03 04:08:00 +00:00
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h	R600/SI: Add VI instructions	2014-12-07 12:18:57 +00:00
AMDGPUTargetMachine.cpp	[CodeGen] Add print and verify pass after each MachineFunctionPass by default	2014-12-11 21:26:47 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
CaymanInstructions.td
CIInstructions.td	R600/SI: Add VI instructions	2014-12-07 12:18:57 +00:00
CMakeLists.txt
EvergreenInstructions.td
LLVMBuild.txt
Makefile
Processors.td	R600/SI: Add VI instructions	2014-12-07 12:18:57 +00:00
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td
R600Intrinsics.td
R600ISelLowering.cpp
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixSGPRCopies.cpp	R600/SI: Fix SIFixSGPRCopies for copies to physical registers	2014-12-03 05:22:39 +00:00
SIFixSGPRLiveRanges.cpp
SIFoldOperands.cpp
SIInsertWaits.cpp	R600/SI: Disable VMEM and SMEM clauses by breaking them with S_NOP	2014-12-07 17:17:43 +00:00
SIInstrFormats.td	R600/SI: Add VI instructions	2014-12-07 12:18:57 +00:00
SIInstrInfo.cpp	R600/SI: Set 20-bit immediate byte offset for SMRD on VI	2014-12-07 17:17:38 +00:00
SIInstrInfo.h	R600/SI: Set 20-bit immediate byte offset for SMRD on VI	2014-12-07 17:17:38 +00:00
SIInstrInfo.td	R600/SI: Set MayStore = 0 on MUBUF loads	2014-12-09 00:03:54 +00:00
SIInstructions.td	R600/SI: Set 20-bit immediate byte offset for SMRD on VI	2014-12-07 17:17:38 +00:00
SIIntrinsics.td
SIISelLowering.cpp	R600/SI: Use getTargetConstant in AdjustRegClass	2014-12-10 19:25:31 +00:00
SIISelLowering.h
SILoadStoreOptimizer.cpp	R600/SI: Fix live range error hidden by SIFoldOperands	2014-12-03 05:22:29 +00:00
SILowerControlFlow.cpp
SILowerI1Copies.cpp	R600/SI: Remove i1 pseudo VALU ops	2014-12-03 05:22:35 +00:00
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp
SIRegisterInfo.h
SIRegisterInfo.td
SISchedule.td
SIShrinkInstructions.cpp	R600/SI: Move continue after checking s_mov_b32.	2014-12-08 19:55:43 +00:00
SITypeRewriter.cpp
VIInstrFormats.td	R600/SI: Add VI instructions	2014-12-07 12:18:57 +00:00
VIInstructions.td	R600/SI: Set 20-bit immediate byte offset for SMRD on VI	2014-12-07 17:17:38 +00:00