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ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
825 lines
32 KiB
C++
825 lines
32 KiB
C++
//===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the ScheduleDAGInstrs class, which implements re-scheduling
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// of MachineInstrs.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched-instrs"
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#include "ScheduleDAGInstrs.h"
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#include "llvm/Operator.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/SmallSet.h"
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using namespace llvm;
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt,
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bool IsPostRAFlag,
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LiveIntervals *lis)
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: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
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InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
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LIS(lis), UnitLatencies(false), LoopRegs(MLI, MDT), FirstDbgValue(0) {
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assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
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DbgValues.clear();
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assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
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"Virtual registers must be removed prior to PostRA scheduling");
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}
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/// getUnderlyingObjectFromInt - This is the function that does the work of
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/// looking through basic ptrtoint+arithmetic+inttoptr sequences.
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static const Value *getUnderlyingObjectFromInt(const Value *V) {
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do {
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if (const Operator *U = dyn_cast<Operator>(V)) {
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// If we find a ptrtoint, we can transfer control back to the
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// regular getUnderlyingObjectFromInt.
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if (U->getOpcode() == Instruction::PtrToInt)
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return U->getOperand(0);
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// If we find an add of a constant or a multiplied value, it's
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// likely that the other operand will lead us to the base
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// object. We don't have to worry about the case where the
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// object address is somehow being computed by the multiply,
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// because our callers only care when the result is an
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// identifibale object.
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if (U->getOpcode() != Instruction::Add ||
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(!isa<ConstantInt>(U->getOperand(1)) &&
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Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
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return V;
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V = U->getOperand(0);
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} else {
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return V;
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}
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assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
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} while (1);
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}
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/// getUnderlyingObject - This is a wrapper around GetUnderlyingObject
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/// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
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static const Value *getUnderlyingObject(const Value *V) {
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// First just call Value::getUnderlyingObject to let it do what it does.
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do {
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V = GetUnderlyingObject(V);
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// If it found an inttoptr, use special code to continue climing.
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if (Operator::getOpcode(V) != Instruction::IntToPtr)
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break;
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const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
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// If that succeeded in finding a pointer, continue the search.
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if (!O->getType()->isPointerTy())
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break;
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V = O;
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} while (1);
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return V;
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}
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/// getUnderlyingObjectForInstr - If this machine instr has memory reference
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/// information and it can be tracked to a normal reference to a known
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/// object, return the Value for that object. Otherwise return null.
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static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
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const MachineFrameInfo *MFI,
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bool &MayAlias) {
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MayAlias = true;
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if (!MI->hasOneMemOperand() ||
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!(*MI->memoperands_begin())->getValue() ||
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(*MI->memoperands_begin())->isVolatile())
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return 0;
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const Value *V = (*MI->memoperands_begin())->getValue();
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if (!V)
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return 0;
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V = getUnderlyingObject(V);
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if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
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// For now, ignore PseudoSourceValues which may alias LLVM IR values
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// because the code that uses this function has no way to cope with
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// such aliases.
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if (PSV->isAliased(MFI))
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return 0;
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MayAlias = PSV->mayAlias(MFI);
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return V;
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}
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if (isIdentifiedObject(V))
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return V;
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return 0;
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}
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void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) {
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LoopRegs.Deps.clear();
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if (MachineLoop *ML = MLI.getLoopFor(BB))
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if (BB == ML->getLoopLatch())
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LoopRegs.VisitLoop(ML);
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}
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void ScheduleDAGInstrs::FinishBlock() {
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// Nothing to do.
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}
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/// Initialize the map with the number of registers.
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void ScheduleDAGInstrs::Reg2SUnitsMap::setRegLimit(unsigned Limit) {
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PhysRegSet.setUniverse(Limit);
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SUnits.resize(Limit);
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}
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/// Clear the map without deallocating storage.
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void ScheduleDAGInstrs::Reg2SUnitsMap::clear() {
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for (const_iterator I = reg_begin(), E = reg_end(); I != E; ++I) {
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SUnits[*I].clear();
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}
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PhysRegSet.clear();
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}
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/// Initialize the DAG and common scheduler state for the current scheduling
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/// region. This does not actually create the DAG, only clears it. The
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/// scheduling driver may call BuildSchedGraph multiple times per scheduling
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/// region.
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void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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unsigned endcount) {
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BB = bb;
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Begin = begin;
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InsertPos = end;
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InsertPosIndex = endcount;
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// Check to see if the scheduler cares about latencies.
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UnitLatencies = ForceUnitLatencies();
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ScheduleDAG::clearDAG();
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}
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/// Close the current scheduling region. Don't clear any state in case the
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/// driver wants to refer to the previous scheduling region.
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void ScheduleDAGInstrs::exitRegion() {
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// Nothing to do.
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}
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/// AddSchedBarrierDeps - Add dependencies from instructions in the current
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/// list of instructions being scheduled to scheduling barrier by adding
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/// the exit SU to the register defs and use list. This is because we want to
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/// make sure instructions which define registers that are either used by
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/// the terminator or are live-out are properly scheduled. This is
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/// especially important when the definition latency of the return value(s)
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/// are too high to be hidden by the branch or when the liveout registers
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/// used by instructions in the fallthrough block.
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void ScheduleDAGInstrs::AddSchedBarrierDeps() {
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MachineInstr *ExitMI = InsertPos != BB->end() ? &*InsertPos : 0;
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ExitSU.setInstr(ExitMI);
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bool AllDepKnown = ExitMI &&
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(ExitMI->isCall() || ExitMI->isBarrier());
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if (ExitMI && AllDepKnown) {
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// If it's a call or a barrier, add dependencies on the defs and uses of
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// instruction.
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for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = ExitMI->getOperand(i);
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if (!MO.isReg() || MO.isDef()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (TRI->isPhysicalRegister(Reg))
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Uses[Reg].push_back(&ExitSU);
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else
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assert(!IsPostRA && "Virtual register encountered after regalloc.");
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}
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} else {
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// For others, e.g. fallthrough, conditional branch, assume the exit
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// uses all the registers that are livein to the successor blocks.
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SmallSet<unsigned, 8> Seen;
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for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
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SE = BB->succ_end(); SI != SE; ++SI)
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for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
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E = (*SI)->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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if (Seen.insert(Reg))
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Uses[Reg].push_back(&ExitSU);
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}
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}
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}
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/// MO is an operand of SU's instruction that defines a physical register. Add
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/// data dependencies from SU to any uses of the physical register.
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void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU,
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const MachineOperand &MO) {
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assert(MO.isDef() && "expect physreg def");
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// Ask the target if address-backscheduling is desirable, and if so how much.
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const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
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unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
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unsigned DataLatency = SU->Latency;
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for (const uint16_t *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) {
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if (!Uses.contains(*Alias))
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continue;
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std::vector<SUnit*> &UseList = Uses[*Alias];
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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if (UseSU == SU)
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continue;
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unsigned LDataLatency = DataLatency;
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// Optionally add in a special extra latency for nodes that
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// feed addresses.
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// TODO: Perhaps we should get rid of
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// SpecialAddressLatency and just move this into
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// adjustSchedDependency for the targets that care about it.
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if (SpecialAddressLatency != 0 && !UnitLatencies &&
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UseSU != &ExitSU) {
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MachineInstr *UseMI = UseSU->getInstr();
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const MCInstrDesc &UseMCID = UseMI->getDesc();
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int RegUseIndex = UseMI->findRegisterUseOperandIdx(*Alias);
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assert(RegUseIndex >= 0 && "UseMI doesn't use register!");
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if (RegUseIndex >= 0 &&
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(UseMI->mayLoad() || UseMI->mayStore()) &&
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(unsigned)RegUseIndex < UseMCID.getNumOperands() &&
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UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
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LDataLatency += SpecialAddressLatency;
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}
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// Adjust the dependence latency using operand def/use
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// information (if any), and then allow the target to
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// perform its own adjustments.
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const SDep& dep = SDep(SU, SDep::Data, LDataLatency, *Alias);
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if (!UnitLatencies) {
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ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
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}
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UseSU->addPred(dep);
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}
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}
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}
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/// addPhysRegDeps - Add register dependencies (data, anti, and output) from
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/// this SUnit to following instructions in the same scheduling region that
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/// depend the physical register referenced at OperIdx.
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void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
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const MachineInstr *MI = SU->getInstr();
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const MachineOperand &MO = MI->getOperand(OperIdx);
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// Optionally add output and anti dependencies. For anti
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// dependencies we use a latency of 0 because for a multi-issue
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// target we want to allow the defining instruction to issue
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// in the same cycle as the using instruction.
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// TODO: Using a latency of 1 here for output dependencies assumes
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// there's no cost for reusing registers.
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SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
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for (const uint16_t *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) {
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if (!Defs.contains(*Alias))
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continue;
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std::vector<SUnit *> &DefList = Defs[*Alias];
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for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
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SUnit *DefSU = DefList[i];
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if (DefSU == &ExitSU)
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continue;
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if (DefSU != SU &&
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(Kind != SDep::Output || !MO.isDead() ||
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!DefSU->getInstr()->registerDefIsDead(*Alias))) {
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if (Kind == SDep::Anti)
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DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
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else {
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unsigned AOLat = TII->getOutputLatency(InstrItins, MI, OperIdx,
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DefSU->getInstr());
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DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
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}
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}
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}
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}
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if (!MO.isDef()) {
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// Either insert a new Reg2SUnits entry with an empty SUnits list, or
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// retrieve the existing SUnits list for this register's uses.
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// Push this SUnit on the use list.
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Uses[MO.getReg()].push_back(SU);
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}
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else {
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addPhysRegDataDeps(SU, MO);
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// Either insert a new Reg2SUnits entry with an empty SUnits list, or
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// retrieve the existing SUnits list for this register's defs.
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std::vector<SUnit *> &DefList = Defs[MO.getReg()];
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// If a def is going to wrap back around to the top of the loop,
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// backschedule it.
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if (!UnitLatencies && DefList.empty()) {
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LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(MO.getReg());
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if (I != LoopRegs.Deps.end()) {
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const MachineOperand *UseMO = I->second.first;
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unsigned Count = I->second.second;
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const MachineInstr *UseMI = UseMO->getParent();
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unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
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const MCInstrDesc &UseMCID = UseMI->getDesc();
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const TargetSubtargetInfo &ST =
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TM.getSubtarget<TargetSubtargetInfo>();
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unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
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// TODO: If we knew the total depth of the region here, we could
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// handle the case where the whole loop is inside the region but
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// is large enough that the isScheduleHigh trick isn't needed.
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if (UseMOIdx < UseMCID.getNumOperands()) {
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// Currently, we only support scheduling regions consisting of
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// single basic blocks. Check to see if the instruction is in
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// the same region by checking to see if it has the same parent.
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if (UseMI->getParent() != MI->getParent()) {
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unsigned Latency = SU->Latency;
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if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass())
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Latency += SpecialAddressLatency;
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// This is a wild guess as to the portion of the latency which
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// will be overlapped by work done outside the current
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// scheduling region.
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Latency -= std::min(Latency, Count);
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// Add the artificial edge.
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ExitSU.addPred(SDep(SU, SDep::Order, Latency,
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/*Reg=*/0, /*isNormalMemory=*/false,
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/*isMustAlias=*/false,
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/*isArtificial=*/true));
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} else if (SpecialAddressLatency > 0 &&
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UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
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// The entire loop body is within the current scheduling region
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// and the latency of this operation is assumed to be greater
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// than the latency of the loop.
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// TODO: Recursively mark data-edge predecessors as
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// isScheduleHigh too.
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SU->isScheduleHigh = true;
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}
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}
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LoopRegs.Deps.erase(I);
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}
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}
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// clear this register's use list
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if (Uses.contains(MO.getReg()))
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Uses[MO.getReg()].clear();
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if (!MO.isDead())
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DefList.clear();
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// Calls will not be reordered because of chain dependencies (see
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// below). Since call operands are dead, calls may continue to be added
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// to the DefList making dependence checking quadratic in the size of
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// the block. Instead, we leave only one call at the back of the
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// DefList.
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if (SU->isCall) {
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while (!DefList.empty() && DefList.back()->isCall)
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DefList.pop_back();
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}
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// Defs are pushed in the order they are visited and never reordered.
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DefList.push_back(SU);
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}
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}
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/// addVRegDefDeps - Add register output and data dependencies from this SUnit
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/// to instructions that occur later in the same scheduling region if they read
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/// from or write to the virtual register defined at OperIdx.
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///
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/// TODO: Hoist loop induction variable increments. This has to be
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/// reevaluated. Generally, IV scheduling should be done before coalescing.
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void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
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const MachineInstr *MI = SU->getInstr();
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unsigned Reg = MI->getOperand(OperIdx).getReg();
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// SSA defs do not have output/anti dependencies.
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// The current operand is a def, so we have at least one.
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if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
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return;
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// Add output dependence to the next nearest def of this vreg.
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//
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// Unless this definition is dead, the output dependence should be
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// transitively redundant with antidependencies from this definition's
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// uses. We're conservative for now until we have a way to guarantee the uses
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// are not eliminated sometime during scheduling. The output dependence edge
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// is also useful if output latency exceeds def-use latency.
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VReg2SUnitMap::iterator DefI = findVRegDef(Reg);
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if (DefI == VRegDefs.end())
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VRegDefs.insert(VReg2SUnit(Reg, SU));
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else {
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SUnit *DefSU = DefI->SU;
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if (DefSU != SU && DefSU != &ExitSU) {
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unsigned OutLatency = TII->getOutputLatency(InstrItins, MI, OperIdx,
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DefSU->getInstr());
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DefSU->addPred(SDep(SU, SDep::Output, OutLatency, Reg));
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}
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DefI->SU = SU;
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}
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}
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/// addVRegUseDeps - Add a register data dependency if the instruction that
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/// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
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/// register antidependency from this SUnit to instructions that occur later in
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/// the same scheduling region if they write the virtual register.
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///
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/// TODO: Handle ExitSU "uses" properly.
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void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
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MachineInstr *MI = SU->getInstr();
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unsigned Reg = MI->getOperand(OperIdx).getReg();
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|
|
// Lookup this operand's reaching definition.
|
|
assert(LIS && "vreg dependencies requires LiveIntervals");
|
|
SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot();
|
|
LiveInterval *LI = &LIS->getInterval(Reg);
|
|
VNInfo *VNI = LI->getVNInfoBefore(UseIdx);
|
|
// VNI will be valid because MachineOperand::readsReg() is checked by caller.
|
|
MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
|
|
// Phis and other noninstructions (after coalescing) have a NULL Def.
|
|
if (Def) {
|
|
SUnit *DefSU = getSUnit(Def);
|
|
if (DefSU) {
|
|
// The reaching Def lives within this scheduling region.
|
|
// Create a data dependence.
|
|
//
|
|
// TODO: Handle "special" address latencies cleanly.
|
|
const SDep &dep = SDep(DefSU, SDep::Data, DefSU->Latency, Reg);
|
|
if (!UnitLatencies) {
|
|
// Adjust the dependence latency using operand def/use information, then
|
|
// allow the target to perform its own adjustments.
|
|
ComputeOperandLatency(DefSU, SU, const_cast<SDep &>(dep));
|
|
const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
|
|
ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
|
|
}
|
|
SU->addPred(dep);
|
|
}
|
|
}
|
|
|
|
// Add antidependence to the following def of the vreg it uses.
|
|
VReg2SUnitMap::iterator DefI = findVRegDef(Reg);
|
|
if (DefI != VRegDefs.end() && DefI->SU != SU)
|
|
DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg));
|
|
}
|
|
|
|
/// Create an SUnit for each real instruction, numbered in top-down toplological
|
|
/// order. The instruction order A < B, implies that no edge exists from B to A.
|
|
///
|
|
/// Map each real instruction to its SUnit.
|
|
///
|
|
/// After initSUnits, the SUnits vector is cannot be resized and the scheduler
|
|
/// may hang onto SUnit pointers. We may relax this in the future by using SUnit
|
|
/// IDs instead of pointers.
|
|
void ScheduleDAGInstrs::initSUnits() {
|
|
// We'll be allocating one SUnit for each real instruction in the region,
|
|
// which is contained within a basic block.
|
|
SUnits.reserve(BB->size());
|
|
|
|
for (MachineBasicBlock::iterator I = Begin; I != InsertPos; ++I) {
|
|
MachineInstr *MI = I;
|
|
if (MI->isDebugValue())
|
|
continue;
|
|
|
|
SUnit *SU = NewSUnit(MI);
|
|
MISUnitMap[MI] = SU;
|
|
|
|
SU->isCall = MI->isCall();
|
|
SU->isCommutable = MI->isCommutable();
|
|
|
|
// Assign the Latency field of SU using target-provided information.
|
|
if (UnitLatencies)
|
|
SU->Latency = 1;
|
|
else
|
|
ComputeLatency(SU);
|
|
}
|
|
}
|
|
|
|
void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
|
|
// Create an SUnit for each real instruction.
|
|
initSUnits();
|
|
|
|
// We build scheduling units by walking a block's instruction list from bottom
|
|
// to top.
|
|
|
|
// Remember where a generic side-effecting instruction is as we procede.
|
|
SUnit *BarrierChain = 0, *AliasChain = 0;
|
|
|
|
// Memory references to specific known memory locations are tracked
|
|
// so that they can be given more precise dependencies. We track
|
|
// separately the known memory locations that may alias and those
|
|
// that are known not to alias
|
|
std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
|
|
std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
|
|
|
|
// Remove any stale debug info; sometimes BuildSchedGraph is called again
|
|
// without emitting the info from the previous call.
|
|
DbgValues.clear();
|
|
FirstDbgValue = NULL;
|
|
|
|
assert(Defs.empty() && Uses.empty() &&
|
|
"Only BuildGraph should update Defs/Uses");
|
|
Defs.setRegLimit(TRI->getNumRegs());
|
|
Uses.setRegLimit(TRI->getNumRegs());
|
|
|
|
assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
|
|
// FIXME: Allow SparseSet to reserve space for the creation of virtual
|
|
// registers during scheduling. Don't artificially inflate the Universe
|
|
// because we want to assert that vregs are not created during DAG building.
|
|
VRegDefs.setUniverse(MRI.getNumVirtRegs());
|
|
|
|
// Model data dependencies between instructions being scheduled and the
|
|
// ExitSU.
|
|
AddSchedBarrierDeps();
|
|
|
|
// Walk the list of instructions, from bottom moving up.
|
|
MachineInstr *PrevMI = NULL;
|
|
for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
|
|
MII != MIE; --MII) {
|
|
MachineInstr *MI = prior(MII);
|
|
if (MI && PrevMI) {
|
|
DbgValues.push_back(std::make_pair(PrevMI, MI));
|
|
PrevMI = NULL;
|
|
}
|
|
|
|
if (MI->isDebugValue()) {
|
|
PrevMI = MI;
|
|
continue;
|
|
}
|
|
|
|
assert(!MI->isTerminator() && !MI->isLabel() &&
|
|
"Cannot schedule terminators or labels!");
|
|
|
|
SUnit *SU = MISUnitMap[MI];
|
|
assert(SU && "No SUnit mapped to this MI");
|
|
|
|
// Add register-based dependencies (data, anti, and output).
|
|
for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
|
|
const MachineOperand &MO = MI->getOperand(j);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
|
|
if (TRI->isPhysicalRegister(Reg))
|
|
addPhysRegDeps(SU, j);
|
|
else {
|
|
assert(!IsPostRA && "Virtual register encountered!");
|
|
if (MO.isDef())
|
|
addVRegDefDeps(SU, j);
|
|
else if (MO.readsReg()) // ignore undef operands
|
|
addVRegUseDeps(SU, j);
|
|
}
|
|
}
|
|
|
|
// Add chain dependencies.
|
|
// Chain dependencies used to enforce memory order should have
|
|
// latency of 0 (except for true dependency of Store followed by
|
|
// aliased Load... we estimate that with a single cycle of latency
|
|
// assuming the hardware will bypass)
|
|
// Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
|
|
// after stack slots are lowered to actual addresses.
|
|
// TODO: Use an AliasAnalysis and do real alias-analysis queries, and
|
|
// produce more precise dependence information.
|
|
#define STORE_LOAD_LATENCY 1
|
|
unsigned TrueMemOrderLatency = 0;
|
|
if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
|
|
(MI->hasVolatileMemoryRef() &&
|
|
(!MI->mayLoad() || !MI->isInvariantLoad(AA)))) {
|
|
// Be conservative with these and add dependencies on all memory
|
|
// references, even those that are known to not alias.
|
|
for (std::map<const Value *, SUnit *>::iterator I =
|
|
NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
|
|
I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
}
|
|
for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
|
|
NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
|
|
for (unsigned i = 0, e = I->second.size(); i != e; ++i)
|
|
I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
|
|
}
|
|
NonAliasMemDefs.clear();
|
|
NonAliasMemUses.clear();
|
|
// Add SU to the barrier chain.
|
|
if (BarrierChain)
|
|
BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
BarrierChain = SU;
|
|
|
|
// fall-through
|
|
new_alias_chain:
|
|
// Chain all possibly aliasing memory references though SU.
|
|
if (AliasChain)
|
|
AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
AliasChain = SU;
|
|
for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
|
|
PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
|
|
for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
|
|
E = AliasMemDefs.end(); I != E; ++I) {
|
|
I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
}
|
|
for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
|
|
AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
|
|
for (unsigned i = 0, e = I->second.size(); i != e; ++i)
|
|
I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
|
|
}
|
|
PendingLoads.clear();
|
|
AliasMemDefs.clear();
|
|
AliasMemUses.clear();
|
|
} else if (MI->mayStore()) {
|
|
bool MayAlias = true;
|
|
TrueMemOrderLatency = STORE_LOAD_LATENCY;
|
|
if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
|
|
// A store to a specific PseudoSourceValue. Add precise dependencies.
|
|
// Record the def in MemDefs, first adding a dep if there is
|
|
// an existing def.
|
|
std::map<const Value *, SUnit *>::iterator I =
|
|
((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
|
|
std::map<const Value *, SUnit *>::iterator IE =
|
|
((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
|
|
if (I != IE) {
|
|
I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
|
|
/*isNormalMemory=*/true));
|
|
I->second = SU;
|
|
} else {
|
|
if (MayAlias)
|
|
AliasMemDefs[V] = SU;
|
|
else
|
|
NonAliasMemDefs[V] = SU;
|
|
}
|
|
// Handle the uses in MemUses, if there are any.
|
|
std::map<const Value *, std::vector<SUnit *> >::iterator J =
|
|
((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
|
|
std::map<const Value *, std::vector<SUnit *> >::iterator JE =
|
|
((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
|
|
if (J != JE) {
|
|
for (unsigned i = 0, e = J->second.size(); i != e; ++i)
|
|
J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency,
|
|
/*Reg=*/0, /*isNormalMemory=*/true));
|
|
J->second.clear();
|
|
}
|
|
if (MayAlias) {
|
|
// Add dependencies from all the PendingLoads, i.e. loads
|
|
// with no underlying object.
|
|
for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
|
|
PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
|
|
// Add dependence on alias chain, if needed.
|
|
if (AliasChain)
|
|
AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
}
|
|
// Add dependence on barrier chain, if needed.
|
|
if (BarrierChain)
|
|
BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
} else {
|
|
// Treat all other stores conservatively.
|
|
goto new_alias_chain;
|
|
}
|
|
|
|
if (!ExitSU.isPred(SU))
|
|
// Push store's up a bit to avoid them getting in between cmp
|
|
// and branches.
|
|
ExitSU.addPred(SDep(SU, SDep::Order, 0,
|
|
/*Reg=*/0, /*isNormalMemory=*/false,
|
|
/*isMustAlias=*/false,
|
|
/*isArtificial=*/true));
|
|
} else if (MI->mayLoad()) {
|
|
bool MayAlias = true;
|
|
TrueMemOrderLatency = 0;
|
|
if (MI->isInvariantLoad(AA)) {
|
|
// Invariant load, no chain dependencies needed!
|
|
} else {
|
|
if (const Value *V =
|
|
getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
|
|
// A load from a specific PseudoSourceValue. Add precise dependencies.
|
|
std::map<const Value *, SUnit *>::iterator I =
|
|
((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
|
|
std::map<const Value *, SUnit *>::iterator IE =
|
|
((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
|
|
if (I != IE)
|
|
I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
|
|
/*isNormalMemory=*/true));
|
|
if (MayAlias)
|
|
AliasMemUses[V].push_back(SU);
|
|
else
|
|
NonAliasMemUses[V].push_back(SU);
|
|
} else {
|
|
// A load with no underlying object. Depend on all
|
|
// potentially aliasing stores.
|
|
for (std::map<const Value *, SUnit *>::iterator I =
|
|
AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
|
|
I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
|
|
PendingLoads.push_back(SU);
|
|
MayAlias = true;
|
|
}
|
|
|
|
// Add dependencies on alias and barrier chains, if needed.
|
|
if (MayAlias && AliasChain)
|
|
AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
if (BarrierChain)
|
|
BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
|
|
}
|
|
}
|
|
}
|
|
if (PrevMI)
|
|
FirstDbgValue = PrevMI;
|
|
|
|
Defs.clear();
|
|
Uses.clear();
|
|
VRegDefs.clear();
|
|
PendingLoads.clear();
|
|
MISUnitMap.clear();
|
|
}
|
|
|
|
void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
|
|
// Compute the latency for the node.
|
|
if (!InstrItins || InstrItins->isEmpty()) {
|
|
SU->Latency = 1;
|
|
|
|
// Simplistic target-independent heuristic: assume that loads take
|
|
// extra time.
|
|
if (SU->getInstr()->mayLoad())
|
|
SU->Latency += 2;
|
|
} else {
|
|
SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr());
|
|
}
|
|
}
|
|
|
|
void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
|
|
SDep& dep) const {
|
|
if (!InstrItins || InstrItins->isEmpty())
|
|
return;
|
|
|
|
// For a data dependency with a known register...
|
|
if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
|
|
return;
|
|
|
|
const unsigned Reg = dep.getReg();
|
|
|
|
// ... find the definition of the register in the defining
|
|
// instruction
|
|
MachineInstr *DefMI = Def->getInstr();
|
|
int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
|
|
if (DefIdx != -1) {
|
|
const MachineOperand &MO = DefMI->getOperand(DefIdx);
|
|
if (MO.isReg() && MO.isImplicit() &&
|
|
DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
|
|
// This is an implicit def, getOperandLatency() won't return the correct
|
|
// latency. e.g.
|
|
// %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
|
|
// %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
|
|
// What we want is to compute latency between def of %D6/%D7 and use of
|
|
// %Q3 instead.
|
|
unsigned Op2 = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
|
|
if (DefMI->getOperand(Op2).isReg())
|
|
DefIdx = Op2;
|
|
}
|
|
MachineInstr *UseMI = Use->getInstr();
|
|
// For all uses of the register, calculate the maxmimum latency
|
|
int Latency = -1;
|
|
if (UseMI) {
|
|
for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = UseMI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isUse())
|
|
continue;
|
|
unsigned MOReg = MO.getReg();
|
|
if (MOReg != Reg)
|
|
continue;
|
|
|
|
int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
|
|
UseMI, i);
|
|
Latency = std::max(Latency, UseCycle);
|
|
}
|
|
} else {
|
|
// UseMI is null, then it must be a scheduling barrier.
|
|
if (!InstrItins || InstrItins->isEmpty())
|
|
return;
|
|
unsigned DefClass = DefMI->getDesc().getSchedClass();
|
|
Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
|
|
}
|
|
|
|
// If we found a latency, then replace the existing dependence latency.
|
|
if (Latency >= 0)
|
|
dep.setLatency(Latency);
|
|
}
|
|
}
|
|
|
|
void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
|
|
SU->getInstr()->dump();
|
|
}
|
|
|
|
std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
|
|
std::string s;
|
|
raw_string_ostream oss(s);
|
|
if (SU == &EntrySU)
|
|
oss << "<entry>";
|
|
else if (SU == &ExitSU)
|
|
oss << "<exit>";
|
|
else
|
|
SU->getInstr()->print(oss);
|
|
return oss.str();
|
|
}
|
|
|
|
/// Return the basic block label. It is not necessarilly unique because a block
|
|
/// contains multiple scheduling regions. But it is fine for visualization.
|
|
std::string ScheduleDAGInstrs::getDAGName() const {
|
|
return "dag." + BB->getFullName();
|
|
}
|