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https://github.com/c64scene-ar/llvm-6502.git
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f74a429816
There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
197 lines
6.5 KiB
C++
197 lines
6.5 KiB
C++
//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the ARM target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMBASEINFO_H
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#define ARMBASEINFO_H
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#include "llvm/Support/ErrorHandling.h"
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// Note that the following auto-generated files only defined enum types, and
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// so are safe to include here.
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// Defines symbolic names for ARM registers. This defines a mapping from
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// register name to register number.
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//
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#include "ARMGenRegisterNames.inc"
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// Defines symbolic names for the ARM instructions.
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//
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#include "ARMGenInstrNames.inc"
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namespace llvm {
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// Enums corresponding to ARM condition codes
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namespace ARMCC {
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// The CondCodes constants map directly to the 4-bit encoding of the
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// condition field for predicated instructions.
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enum CondCodes { // Meaning (integer) Meaning (floating-point)
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EQ, // Equal Equal
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NE, // Not equal Not equal, or unordered
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HS, // Carry set >, ==, or unordered
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LO, // Carry clear Less than
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MI, // Minus, negative Less than
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PL, // Plus, positive or zero >, ==, or unordered
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VS, // Overflow Unordered
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VC, // No overflow Not unordered
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HI, // Unsigned higher Greater than, or unordered
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LS, // Unsigned lower or same Less than or equal
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GE, // Greater than or equal Greater than or equal
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LT, // Less than Less than, or unordered
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GT, // Greater than Greater than
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LE, // Less than or equal <, ==, or unordered
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AL // Always (unconditional) Always (unconditional)
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};
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inline static CondCodes getOppositeCondition(CondCodes CC) {
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case EQ: return NE;
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case NE: return EQ;
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case HS: return LO;
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case LO: return HS;
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case MI: return PL;
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case PL: return MI;
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case VS: return VC;
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case VC: return VS;
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case HI: return LS;
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case LS: return HI;
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case GE: return LT;
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case LT: return GE;
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case GT: return LE;
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case LE: return GT;
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}
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}
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} // namespace ARMCC
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inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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switch (CC) {
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default: llvm_unreachable("Unknown condition code");
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case ARMCC::EQ: return "eq";
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case ARMCC::NE: return "ne";
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case ARMCC::HS: return "hs";
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case ARMCC::LO: return "lo";
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case ARMCC::MI: return "mi";
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case ARMCC::PL: return "pl";
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case ARMCC::VS: return "vs";
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case ARMCC::VC: return "vc";
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case ARMCC::HI: return "hi";
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case ARMCC::LS: return "ls";
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case ARMCC::GE: return "ge";
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case ARMCC::LT: return "lt";
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case ARMCC::GT: return "gt";
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case ARMCC::LE: return "le";
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case ARMCC::AL: return "al";
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}
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}
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namespace ARM_MB {
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// The Memory Barrier Option constants map directly to the 4-bit encoding of
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// the option field for memory barrier operations.
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enum MemBOpt {
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SY = 15,
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ST = 14,
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ISH = 11,
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ISHST = 10,
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NSH = 7,
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NSHST = 6,
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OSH = 3,
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OSHST = 2
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};
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inline static const char *MemBOptToString(unsigned val) {
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switch (val) {
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default: llvm_unreachable("Unknown memory operation");
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case SY: return "sy";
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case ST: return "st";
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case ISH: return "ish";
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case ISHST: return "ishst";
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case NSH: return "nsh";
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case NSHST: return "nshst";
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case OSH: return "osh";
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case OSHST: return "oshst";
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}
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}
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} // namespace ARM_MB
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/// getARMRegisterNumbering - Given the enum value for some register, e.g.
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/// ARM::LR, return the number that it corresponds to (e.g. 14).
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inline static unsigned getARMRegisterNumbering(unsigned Reg) {
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using namespace ARM;
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switch (Reg) {
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default:
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llvm_unreachable("Unknown ARM register!");
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case R0: case S0: case D0: case Q0: return 0;
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case R1: case S1: case D1: case Q1: return 1;
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case R2: case S2: case D2: case Q2: return 2;
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case R3: case S3: case D3: case Q3: return 3;
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case R4: case S4: case D4: case Q4: return 4;
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case R5: case S5: case D5: case Q5: return 5;
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case R6: case S6: case D6: case Q6: return 6;
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case R7: case S7: case D7: case Q7: return 7;
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case R8: case S8: case D8: case Q8: return 8;
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case R9: case S9: case D9: case Q9: return 9;
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case R10: case S10: case D10: case Q10: return 10;
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case R11: case S11: case D11: case Q11: return 11;
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case R12: case S12: case D12: case Q12: return 12;
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case SP: case S13: case D13: case Q13: return 13;
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case LR: case S14: case D14: case Q14: return 14;
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case PC: case S15: case D15: case Q15: return 15;
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case S16: case D16: return 16;
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case S17: case D17: return 17;
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case S18: case D18: return 18;
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case S19: case D19: return 19;
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case S20: case D20: return 20;
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case S21: case D21: return 21;
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case S22: case D22: return 22;
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case S23: case D23: return 23;
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case S24: case D24: return 24;
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case S25: case D25: return 25;
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case S26: case D26: return 26;
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case S27: case D27: return 27;
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case S28: case D28: return 28;
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case S29: case D29: return 29;
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case S30: case D30: return 30;
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case S31: case D31: return 31;
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}
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}
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namespace ARMII {
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/// Target Operand Flag enum.
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enum TOF {
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//===------------------------------------------------------------------===//
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// ARM Specific MachineOperand flags.
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MO_NO_FLAG,
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/// MO_LO16 - On a symbol operand, this represents a relocation containing
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/// lower 16 bit of the address. Used only via movw instruction.
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MO_LO16,
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/// MO_HI16 - On a symbol operand, this represents a relocation containing
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/// higher 16 bit of the address. Used only via movt instruction.
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MO_HI16,
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/// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
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/// call operand.
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MO_PLT
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};
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} // end namespace ARMII
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} // end namespace llvm;
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#endif
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