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- If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
651 lines
27 KiB
C++
651 lines
27 KiB
C++
//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86INSTRUCTIONINFO_H
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#define X86INSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "X86.h"
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#include "X86RegisterInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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namespace llvm {
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class X86RegisterInfo;
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class X86TargetMachine;
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namespace X86 {
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// X86 specific condition code. These correspond to X86_*_COND in
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// X86InstrInfo.td. They must be kept in synch.
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enum CondCode {
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COND_A = 0,
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COND_AE = 1,
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COND_B = 2,
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COND_BE = 3,
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COND_E = 4,
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COND_G = 5,
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COND_GE = 6,
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COND_L = 7,
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COND_LE = 8,
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COND_NE = 9,
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COND_NO = 10,
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COND_NP = 11,
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COND_NS = 12,
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COND_O = 13,
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COND_P = 14,
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COND_S = 15,
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// Artificial condition codes. These are used by AnalyzeBranch
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// to indicate a block terminated with two conditional branches to
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// the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
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// which can't be represented on x86 with a single condition. These
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// are never used in MachineInstrs.
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COND_NE_OR_P,
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COND_NP_OR_E,
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COND_INVALID
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};
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// Turn condition code into conditional branch opcode.
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unsigned GetCondBranchFromCond(CondCode CC);
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/// GetOppositeBranchCondition - Return the inverse of the specified cond,
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/// e.g. turning COND_E to COND_NE.
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CondCode GetOppositeBranchCondition(X86::CondCode CC);
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}
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/// X86II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace X86II {
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/// Target Operand Flag enum.
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enum TOF {
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//===------------------------------------------------------------------===//
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// X86 Specific MachineOperand flags.
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MO_NO_FLAG,
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/// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
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/// relocation of:
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/// SYMBOL_LABEL + [. - PICBASELABEL]
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MO_GOT_ABSOLUTE_ADDRESS,
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/// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
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/// immediate should get the value of the symbol minus the PIC base label:
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/// SYMBOL_LABEL - PICBASELABEL
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MO_PIC_BASE_OFFSET,
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/// MO_GOT - On a symbol operand this indicates that the immediate is the
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/// offset to the GOT entry for the symbol name from the base of the GOT.
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///
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @GOT
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MO_GOT,
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/// MO_GOTOFF - On a symbol operand this indicates that the immediate is
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/// the offset to the location of the symbol name from the base of the GOT.
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///
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @GOTOFF
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MO_GOTOFF,
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/// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
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/// offset to the GOT entry for the symbol name from the current code
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/// location.
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///
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @GOTPCREL
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MO_GOTPCREL,
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/// MO_PLT - On a symbol operand this indicates that the immediate is
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/// offset to the PLT entry of symbol name from the current code location.
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///
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/// See the X86-64 ELF ABI supplement for more details.
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/// SYMBOL_LABEL @PLT
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MO_PLT,
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/// MO_TLSGD - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @TLSGD
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MO_TLSGD,
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/// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @GOTTPOFF
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MO_GOTTPOFF,
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/// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @INDNTPOFF
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MO_INDNTPOFF,
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/// MO_TPOFF - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @TPOFF
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MO_TPOFF,
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/// MO_NTPOFF - On a symbol operand this indicates that the immediate is
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/// some TLS offset.
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///
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/// See 'ELF Handling for Thread-Local Storage' for more details.
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/// SYMBOL_LABEL @NTPOFF
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MO_NTPOFF,
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/// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
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/// reference is actually to the "__imp_FOO" symbol. This is used for
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/// dllimport linkage on windows.
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MO_DLLIMPORT,
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/// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
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/// reference is actually to the "FOO$stub" symbol. This is used for calls
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/// and jumps to external functions on Tiger and before.
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MO_DARWIN_STUB,
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/// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
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/// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
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/// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
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MO_DARWIN_NONLAZY,
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/// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
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/// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
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/// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
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MO_DARWIN_NONLAZY_PIC_BASE,
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/// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
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/// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
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/// which is a PIC-base-relative reference to a hidden dyld lazy pointer
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/// stub.
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MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
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};
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}
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/// isGlobalStubReference - Return true if the specified TargetFlag operand is
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/// a reference to a stub for a global, not the global itself.
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inline static bool isGlobalStubReference(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_DLLIMPORT: // dllimport stub.
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case X86II::MO_GOTPCREL: // rip-relative GOT reference.
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case X86II::MO_GOT: // normal GOT reference.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
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case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
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return true;
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default:
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return false;
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}
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}
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/// isGlobalRelativeToPICBase - Return true if the specified global value
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/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
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/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
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inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
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case X86II::MO_GOT: // isPICStyleGOT: other global.
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case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
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return true;
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default:
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return false;
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}
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}
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/// X86II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace X86II {
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enum {
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//===------------------------------------------------------------------===//
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// Instruction encodings. These are the standard/most common forms for X86
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// instructions.
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//
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// PseudoFrm - This represents an instruction that is a pseudo instruction
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// or one that has not been implemented yet. It is illegal to code generate
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// it, but tolerated for intermediate implementation stages.
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Pseudo = 0,
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/// Raw - This form is for instructions that don't have any operands, so
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/// they are just a fixed opcode value, like 'leave'.
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RawFrm = 1,
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/// AddRegFrm - This form is used for instructions like 'push r32' that have
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/// their one register operand added to their opcode.
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AddRegFrm = 2,
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/// MRMDestReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is a register.
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///
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MRMDestReg = 3,
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/// MRMDestMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is memory.
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///
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MRMDestMem = 4,
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/// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is a register.
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///
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MRMSrcReg = 5,
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/// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is memory.
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///
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MRMSrcMem = 6,
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/// MRM[0-7][rm] - These forms are used to represent instructions that use
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/// a Mod/RM byte, and use the middle field to hold extended opcode
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/// information. In the intel manual these are represented as /0, /1, ...
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///
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// First, instructions that operate on a register r/m operand...
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MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
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MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
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// Next, instructions that operate on a memory r/m operand...
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MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
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MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
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// MRMInitReg - This form is used for instructions whose source and
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// destinations are the same register.
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MRMInitReg = 32,
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FormMask = 63,
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//===------------------------------------------------------------------===//
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// Actual flags...
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// OpSize - Set if this instruction requires an operand size prefix (0x66),
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// which most often indicates that the instruction operates on 16 bit data
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// instead of 32 bit data.
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OpSize = 1 << 6,
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// AsSize - Set if this instruction requires an operand size prefix (0x67),
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// which most often indicates that the instruction address 16 bit address
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// instead of 32 bit address (or 32 bit address in 64 bit mode).
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AdSize = 1 << 7,
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//===------------------------------------------------------------------===//
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// Op0Mask - There are several prefix bytes that are used to form two byte
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// opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
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// used to obtain the setting of this field. If no bits in this field is
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// set, there is no prefix byte for obtaining a multibyte opcode.
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//
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Op0Shift = 8,
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Op0Mask = 0xF << Op0Shift,
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// TB - TwoByte - Set if this instruction has a two byte opcode, which
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// starts with a 0x0F byte before the real opcode.
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TB = 1 << Op0Shift,
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// REP - The 0xF3 prefix byte indicating repetition of the following
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// instruction.
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REP = 2 << Op0Shift,
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// D8-DF - These escape opcodes are used by the floating point unit. These
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// values must remain sequential.
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D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
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DA = 5 << Op0Shift, DB = 6 << Op0Shift,
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DC = 7 << Op0Shift, DD = 8 << Op0Shift,
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DE = 9 << Op0Shift, DF = 10 << Op0Shift,
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// XS, XD - These prefix codes are for single and double precision scalar
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// floating point operations performed in the SSE registers.
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XD = 11 << Op0Shift, XS = 12 << Op0Shift,
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// T8, TA - Prefix after the 0x0F prefix.
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T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
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// TF - Prefix before and after 0x0F
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TF = 15 << Op0Shift,
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//===------------------------------------------------------------------===//
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// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
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// They are used to specify GPRs and SSE registers, 64-bit operand size,
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// etc. We only cares about REX.W and REX.R bits and only the former is
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// statically determined.
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//
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REXShift = 12,
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REX_W = 1 << REXShift,
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//===------------------------------------------------------------------===//
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// This three-bit field describes the size of an immediate operand. Zero is
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// unused so that we can tell if we forgot to set a value.
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ImmShift = 13,
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ImmMask = 7 << ImmShift,
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Imm8 = 1 << ImmShift,
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Imm16 = 2 << ImmShift,
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Imm32 = 3 << ImmShift,
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Imm64 = 4 << ImmShift,
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//===------------------------------------------------------------------===//
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// FP Instruction Classification... Zero is non-fp instruction.
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// FPTypeMask - Mask for all of the FP types...
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FPTypeShift = 16,
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FPTypeMask = 7 << FPTypeShift,
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// NotFP - The default, set for instructions that do not use FP registers.
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NotFP = 0 << FPTypeShift,
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// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
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ZeroArgFP = 1 << FPTypeShift,
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// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
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OneArgFP = 2 << FPTypeShift,
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// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
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// result back to ST(0). For example, fcos, fsqrt, etc.
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//
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OneArgFPRW = 3 << FPTypeShift,
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// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
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// explicit argument, storing the result to either ST(0) or the implicit
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// argument. For example: fadd, fsub, fmul, etc...
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TwoArgFP = 4 << FPTypeShift,
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// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
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// explicit argument, but have no destination. Example: fucom, fucomi, ...
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CompareFP = 5 << FPTypeShift,
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// CondMovFP - "2 operand" floating point conditional move instructions.
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CondMovFP = 6 << FPTypeShift,
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// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
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SpecialFP = 7 << FPTypeShift,
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// Lock prefix
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LOCKShift = 19,
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LOCK = 1 << LOCKShift,
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// Segment override prefixes. Currently we just need ability to address
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// stuff in gs and fs segments.
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SegOvrShift = 20,
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SegOvrMask = 3 << SegOvrShift,
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FS = 1 << SegOvrShift,
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GS = 2 << SegOvrShift,
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// Bits 22 -> 23 are unused
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OpcodeShift = 24,
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OpcodeMask = 0xFF << OpcodeShift
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};
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}
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const int X86AddrNumOperands = 5;
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inline static bool isScale(const MachineOperand &MO) {
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return MO.isImm() &&
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(MO.getImm() == 1 || MO.getImm() == 2 ||
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MO.getImm() == 4 || MO.getImm() == 8);
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}
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inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFI()) return true;
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isReg() &&
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(MI->getOperand(Op+3).isImm() ||
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MI->getOperand(Op+3).isGlobal() ||
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MI->getOperand(Op+3).isCPI() ||
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MI->getOperand(Op+3).isJTI());
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}
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inline static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFI()) return true;
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return Op+5 <= MI->getNumOperands() &&
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MI->getOperand(Op+4).isReg() &&
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isLeaMem(MI, Op);
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}
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class X86InstrInfo : public TargetInstrInfoImpl {
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X86TargetMachine &TM;
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const X86RegisterInfo RI;
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/// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
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/// RegOp2MemOpTable2 - Load / store folding opcode maps.
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///
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DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr;
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DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0;
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DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1;
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DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2;
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/// MemOp2RegOpTable - Load / store unfolding opcode map.
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///
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DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
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public:
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explicit X86InstrInfo(X86TargetMachine &tm);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
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/// Return true if the instruction is a register to register move and return
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/// the source and dest operands and their sub-register indices by reference.
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virtual bool isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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/// hasLoadFromStackSlot - If the specified machine instruction has
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/// a load from a stack slot, return true along with the FrameIndex
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/// of the loaded stack slot. If not, return false. Unlike
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/// isLoadFromStackSlot, this returns true for any instructions that
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/// loads from the stack. This is a hint only and may not catch all
|
|
/// cases.
|
|
bool hasLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
|
|
|
|
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
|
|
/// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
|
|
/// stack locations as well. This uses a heuristic so it isn't
|
|
/// reliable for correctness.
|
|
unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
|
|
int &FrameIndex) const;
|
|
|
|
/// hasStoreToStackSlot - If the specified machine instruction has a
|
|
/// store to a stack slot, return true along with the FrameIndex of
|
|
/// the loaded stack slot. If not, return false. Unlike
|
|
/// isStoreToStackSlot, this returns true for any instructions that
|
|
/// loads from the stack. This is a hint only and may not catch all
|
|
/// cases.
|
|
bool hasStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
|
|
|
|
bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
|
|
AliasAnalysis *AA) const;
|
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, unsigned SubIdx,
|
|
const MachineInstr *Orig,
|
|
const TargetRegisterInfo *TRI) const;
|
|
|
|
/// convertToThreeAddress - This method must be implemented by targets that
|
|
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
|
|
/// may be able to convert a two-address instruction into a true
|
|
/// three-address instruction on demand. This allows the X86 target (for
|
|
/// example) to convert ADD and SHL instructions into LEA instructions if they
|
|
/// would require register copies due to two-addressness.
|
|
///
|
|
/// This method returns a null pointer if the transformation cannot be
|
|
/// performed, otherwise it returns the new instruction.
|
|
///
|
|
virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
|
|
MachineBasicBlock::iterator &MBBI,
|
|
LiveVariables *LV) const;
|
|
|
|
/// commuteInstruction - We have a few instructions that must be hacked on to
|
|
/// commute them.
|
|
///
|
|
virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
|
|
|
|
// Branch analysis.
|
|
virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
|
|
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
MachineBasicBlock *&FBB,
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
bool AllowModify) const;
|
|
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
|
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB,
|
|
const SmallVectorImpl<MachineOperand> &Cond) const;
|
|
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, unsigned SrcReg,
|
|
const TargetRegisterClass *DestRC,
|
|
const TargetRegisterClass *SrcRC) const;
|
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
const TargetRegisterClass *RC) const;
|
|
|
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
const TargetRegisterClass *RC,
|
|
MachineInstr::mmo_iterator MMOBegin,
|
|
MachineInstr::mmo_iterator MMOEnd,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
|
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, int FrameIndex,
|
|
const TargetRegisterClass *RC) const;
|
|
|
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
const TargetRegisterClass *RC,
|
|
MachineInstr::mmo_iterator MMOBegin,
|
|
MachineInstr::mmo_iterator MMOEnd,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
|
|
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
|
|
|
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
|
|
|
/// foldMemoryOperand - If this target supports it, fold a load or store of
|
|
/// the specified stack slot into the specified machine instruction for the
|
|
/// specified operand(s). If this is possible, the target should perform the
|
|
/// folding and return true, otherwise it should return false. If it folds
|
|
/// the instruction, it is likely that the MachineInstruction the iterator
|
|
/// references has been changed.
|
|
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
MachineInstr* MI,
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
int FrameIndex) const;
|
|
|
|
/// foldMemoryOperand - Same as the previous version except it allows folding
|
|
/// of any load and store from / to any address, not just from a specific
|
|
/// stack slot.
|
|
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
MachineInstr* MI,
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
MachineInstr* LoadMI) const;
|
|
|
|
/// canFoldMemoryOperand - Returns true if the specified load / store is
|
|
/// folding is possible.
|
|
virtual bool canFoldMemoryOperand(const MachineInstr*,
|
|
const SmallVectorImpl<unsigned> &) const;
|
|
|
|
/// unfoldMemoryOperand - Separate a single instruction which folded a load or
|
|
/// a store or a load and a store into two or more instruction. If this is
|
|
/// possible, returns true as well as the new instructions by reference.
|
|
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
|
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
|
|
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
|
SmallVectorImpl<SDNode*> &NewNodes) const;
|
|
|
|
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
|
|
/// instruction after load / store are unfolded from an instruction of the
|
|
/// specified opcode. It returns zero if the specified unfolding is not
|
|
/// possible. If LoadRegIndex is non-null, it is filled in with the operand
|
|
/// index of the operand which will hold the register holding the loaded
|
|
/// value.
|
|
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
|
bool UnfoldLoad, bool UnfoldStore,
|
|
unsigned *LoadRegIndex = 0) const;
|
|
|
|
virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
|
|
virtual
|
|
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
|
|
|
/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
|
|
/// instruction that defines the specified register class.
|
|
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
|
|
|
|
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
|
|
// specified machine instruction.
|
|
//
|
|
unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
|
|
return TID->TSFlags >> X86II::OpcodeShift;
|
|
}
|
|
unsigned char getBaseOpcodeFor(unsigned Opcode) const {
|
|
return getBaseOpcodeFor(&get(Opcode));
|
|
}
|
|
|
|
static bool isX86_64NonExtLowByteReg(unsigned reg) {
|
|
return (reg == X86::SPL || reg == X86::BPL ||
|
|
reg == X86::SIL || reg == X86::DIL);
|
|
}
|
|
|
|
static unsigned sizeOfImm(const TargetInstrDesc *Desc);
|
|
static bool isX86_64ExtendedReg(const MachineOperand &MO);
|
|
static unsigned determineREX(const MachineInstr &MI);
|
|
|
|
/// GetInstSize - Returns the size of the specified MachineInstr.
|
|
///
|
|
virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
|
|
|
|
/// getGlobalBaseReg - Return a virtual register initialized with the
|
|
/// the global base register value. Output instructions required to
|
|
/// initialize the register in the function entry block, if necessary.
|
|
///
|
|
unsigned getGlobalBaseReg(MachineFunction *MF) const;
|
|
|
|
private:
|
|
MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
MachineInstr* MI,
|
|
unsigned OpNum,
|
|
const SmallVectorImpl<MachineOperand> &MOs,
|
|
unsigned Size, unsigned Alignment) const;
|
|
|
|
/// isFrameOperand - Return true and the FrameIndex if the specified
|
|
/// operand and follow operands form a reference to the stack frame.
|
|
bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
|
|
int &FrameIndex) const;
|
|
};
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|