mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
2.6 KiB
LLVM
85 lines
2.6 KiB
LLVM
; RUN: opt < %s -instcombine -disable-output
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; SimplifyDemandedBits should cope with pointer types.
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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%struct.VEC_rtx_base = type { i32, i32, [1 x %struct.rtx_def*] }
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%struct.VEC_rtx_gc = type { %struct.VEC_rtx_base }
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%struct.block_symbol = type { [3 x %struct.rtunion], %struct.object_block*, i64 }
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%struct.object_block = type { %struct.section*, i32, i64, %struct.VEC_rtx_gc*, %struct.VEC_rtx_gc* }
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%struct.omp_clause_subcode = type { i32 }
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%struct.rtunion = type { i8* }
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%struct.rtx_def = type { i16, i8, i8, %struct.u }
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%struct.section = type { %struct.unnamed_section }
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%struct.u = type { %struct.block_symbol }
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%struct.unnamed_section = type { %struct.omp_clause_subcode, void (i8*)*, i8*, %struct.section* }
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define fastcc void @cse_insn(%struct.rtx_def* %insn, %struct.rtx_def* %libcall_insn) nounwind {
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entry:
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br i1 undef, label %bb43, label %bb88
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bb43: ; preds = %entry
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br label %bb88
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bb88: ; preds = %bb43, %entry
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br i1 undef, label %bb95, label %bb107
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bb95: ; preds = %bb88
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unreachable
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bb107: ; preds = %bb88
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%0 = load i16, i16* undef, align 8 ; <i16> [#uses=1]
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%1 = icmp eq i16 %0, 38 ; <i1> [#uses=1]
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%src_eqv_here.0 = select i1 %1, %struct.rtx_def* null, %struct.rtx_def* null ; <%struct.rtx_def*> [#uses=1]
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br i1 undef, label %bb127, label %bb125
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bb125: ; preds = %bb107
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br i1 undef, label %bb127, label %bb126
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bb126: ; preds = %bb125
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br i1 undef, label %bb129, label %bb133
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bb127: ; preds = %bb125, %bb107
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unreachable
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bb129: ; preds = %bb126
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br label %bb133
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bb133: ; preds = %bb129, %bb126
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br i1 undef, label %bb134, label %bb146
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bb134: ; preds = %bb133
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unreachable
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bb146: ; preds = %bb133
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br i1 undef, label %bb180, label %bb186
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bb180: ; preds = %bb146
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%2 = icmp eq %struct.rtx_def* null, null ; <i1> [#uses=1]
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%3 = zext i1 %2 to i8 ; <i8> [#uses=1]
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%4 = icmp ne %struct.rtx_def* %src_eqv_here.0, null ; <i1> [#uses=1]
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%5 = zext i1 %4 to i8 ; <i8> [#uses=1]
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%toBool181 = icmp ne i8 %3, 0 ; <i1> [#uses=1]
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%toBool182 = icmp ne i8 %5, 0 ; <i1> [#uses=1]
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%6 = and i1 %toBool181, %toBool182 ; <i1> [#uses=1]
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%7 = zext i1 %6 to i8 ; <i8> [#uses=1]
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%toBool183 = icmp ne i8 %7, 0 ; <i1> [#uses=1]
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br i1 %toBool183, label %bb184, label %bb186
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bb184: ; preds = %bb180
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br i1 undef, label %bb185, label %bb186
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bb185: ; preds = %bb184
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br label %bb186
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bb186: ; preds = %bb185, %bb184, %bb180, %bb146
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br i1 undef, label %bb190, label %bb195
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bb190: ; preds = %bb186
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unreachable
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bb195: ; preds = %bb186
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unreachable
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}
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