mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-28 04:33:05 +00:00
f6713916fb
Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
17 lines
435 B
LLVM
17 lines
435 B
LLVM
; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=linearscan | FileCheck %s
|
|
; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=basic | FileCheck %s
|
|
|
|
; The greedy register allocator uses a single CSR here, invalidating the test.
|
|
|
|
@b = external global i64*
|
|
|
|
define i64 @t(i64 %a) nounwind readonly {
|
|
entry:
|
|
; CHECK: push {lr}
|
|
; CHECK: pop {lr}
|
|
%0 = load i64** @b, align 4
|
|
%1 = load i64* %0, align 4
|
|
%2 = mul i64 %1, %a
|
|
ret i64 %2
|
|
}
|