mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
563 B
LLVM
25 lines
563 B
LLVM
; RUN: llc < %s -march=ptx32 | FileCheck %s
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; preds
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define ptx_device i32 @t1_and_preds(i1 %x, i1 %y) {
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; CHECK: and.pred p{{[0-9]+}}, p{{[0-9]+}}, p{{[0-9]+}}
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%c = and i1 %x, %y
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%d = zext i1 %c to i32
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ret i32 %d
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}
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define ptx_device i32 @t1_or_preds(i1 %x, i1 %y) {
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; CHECK: or.pred p{{[0-9]+}}, p{{[0-9]+}}, p{{[0-9]+}}
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%a = or i1 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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define ptx_device i32 @t1_xor_preds(i1 %x, i1 %y) {
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; CHECK: xor.pred p{{[0-9]+}}, p{{[0-9]+}}, p{{[0-9]+}}
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%a = xor i1 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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