mirror of
https://github.com/c64scene-ar/llvm-6502.git
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efficiency. Fix a few formatting bugs along the way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76601 91177308-0d34-0410-b5e6-96231b3b80d8
939 lines
34 KiB
C++
939 lines
34 KiB
C++
//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is emits an assembly printer for the current target.
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// Note that this is currently fairly skeletal, but will grow over time.
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//
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//===----------------------------------------------------------------------===//
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#include "AsmWriterEmitter.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include <algorithm>
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#include <sstream>
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#include <iostream>
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using namespace llvm;
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static bool isIdentChar(char C) {
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return (C >= 'a' && C <= 'z') ||
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(C >= 'A' && C <= 'Z') ||
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(C >= '0' && C <= '9') ||
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C == '_';
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}
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// This should be an anon namespace, this works around a GCC warning.
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namespace llvm {
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struct AsmWriterOperand {
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enum OpType {
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isLiteralTextOperand,
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isMachineInstrOperand,
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isLiteralStatementOperand
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} OperandType;
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/// Str - For isLiteralTextOperand, this IS the literal text. For
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/// isMachineInstrOperand, this is the PrinterMethodName for the operand.
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std::string Str;
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/// MiOpNo - For isMachineInstrOperand, this is the operand number of the
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/// machine instruction.
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unsigned MIOpNo;
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/// MiModifier - For isMachineInstrOperand, this is the modifier string for
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/// an operand, specified with syntax like ${opname:modifier}.
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std::string MiModifier;
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// To make VS STL happy
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AsmWriterOperand(OpType op = isLiteralTextOperand):OperandType(op) {}
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AsmWriterOperand(const std::string &LitStr,
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OpType op = isLiteralTextOperand)
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: OperandType(op), Str(LitStr) {}
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AsmWriterOperand(const std::string &Printer, unsigned OpNo,
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const std::string &Modifier,
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OpType op = isMachineInstrOperand)
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: OperandType(op), Str(Printer), MIOpNo(OpNo),
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MiModifier(Modifier) {}
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bool operator!=(const AsmWriterOperand &Other) const {
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if (OperandType != Other.OperandType || Str != Other.Str) return true;
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if (OperandType == isMachineInstrOperand)
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return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
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return false;
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}
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bool operator==(const AsmWriterOperand &Other) const {
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return !operator!=(Other);
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}
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/// getCode - Return the code that prints this operand.
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std::string getCode() const;
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};
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}
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namespace llvm {
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class AsmWriterInst {
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public:
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std::vector<AsmWriterOperand> Operands;
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const CodeGenInstruction *CGI;
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/// MAX_GROUP_NESTING_LEVEL - The maximum number of group nesting
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/// levels we ever expect to see in an asm operand.
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static const int MAX_GROUP_NESTING_LEVEL = 10;
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/// GroupLevel - The level of nesting of the current operand
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/// group, such as [reg + (reg + offset)]. -1 means we are not in
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/// a group.
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int GroupLevel;
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/// GroupDelim - Remember the delimeter for a group operand.
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char GroupDelim[MAX_GROUP_NESTING_LEVEL];
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/// ReadingWhitespace - Tell whether we just read some whitespace.
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bool ReadingWhitespace;
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/// InGroup - Determine whether we are in the middle of an
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/// operand group.
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bool InGroup() const { return GroupLevel != -1; }
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/// InWhitespace - Determine whether we are in the middle of
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/// emitting whitespace.
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bool InWhitespace() const { return ReadingWhitespace; }
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AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant);
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/// MatchesAllButOneOp - If this instruction is exactly identical to the
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/// specified instruction except for one differing operand, return the
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/// differing operand number. Otherwise return ~0.
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unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
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private:
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void AddLiteralString(const std::string &Str) {
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// If the last operand was already a literal text string, append this to
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// it, otherwise add a new operand.
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if (!Operands.empty() &&
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Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
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Operands.back().Str.append(Str);
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else
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Operands.push_back(AsmWriterOperand(Str));
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}
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};
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}
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std::string AsmWriterOperand::getCode() const {
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if (OperandType == isLiteralTextOperand)
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return "O << \"" + Str + "\"; ";
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if (OperandType == isLiteralStatementOperand) {
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return Str;
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}
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if (OperandType == isLiteralStatementOperand) {
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return Str;
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}
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if (OperandType == isLiteralStatementOperand) {
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return Str;
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}
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std::string Result = Str + "(MI";
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if (MIOpNo != ~0U)
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Result += ", " + utostr(MIOpNo);
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if (!MiModifier.empty())
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Result += ", \"" + MiModifier + '"';
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return Result + "); ";
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}
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/// ParseAsmString - Parse the specified Instruction's AsmString into this
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/// AsmWriterInst.
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///
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AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant)
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: GroupLevel(-1), ReadingWhitespace(false) {
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this->CGI = &CGI;
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unsigned CurVariant = ~0U; // ~0 if we are outside a {.|.|.} region, other #.
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// NOTE: Any extensions to this code need to be mirrored in the
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// AsmPrinter::printInlineAsm code that executes as compile time (assuming
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// that inline asm strings should also get the new feature)!
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const std::string &AsmString = CGI.AsmString;
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std::string::size_type LastEmitted = 0;
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while (LastEmitted != AsmString.size()) {
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std::string::size_type DollarPos =
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AsmString.find_first_of("${|}\\", LastEmitted);
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if (DollarPos == std::string::npos) DollarPos = AsmString.size();
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// Emit a constant string fragment.
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// TODO: Recognize an operand separator to determine when to pad
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// to the next operator.
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if (DollarPos != LastEmitted) {
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if (CurVariant == Variant || CurVariant == ~0U) {
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for (; LastEmitted != DollarPos; ++LastEmitted)
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switch (AsmString[LastEmitted]) {
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case '\n':
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assert(!InGroup() && "Missing matching group delimeter");
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ReadingWhitespace = false;
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AddLiteralString("\\n");
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break;
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case '\t':
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if (!InGroup()) {
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ReadingWhitespace = true;
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}
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AddLiteralString("\\t");
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break;
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case '"':
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if (InWhitespace() && !InGroup())
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Operands.push_back(
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AsmWriterOperand(
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"O.PadToColumn(TAI->getOperandColumn(OperandColumn++));\n",
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AsmWriterOperand::isLiteralStatementOperand));
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ReadingWhitespace = false;
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AddLiteralString("\\\"");
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break;
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case '\\':
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if (InWhitespace() && !InGroup())
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Operands.push_back(
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AsmWriterOperand(
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"O.PadToColumn(TAI->getOperandColumn(OperandColumn++));\n",
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AsmWriterOperand::isLiteralStatementOperand));
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ReadingWhitespace = false;
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AddLiteralString("\\\\");
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break;
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case '(': // Fallthrough
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case '[':
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if (InWhitespace() && !InGroup())
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Operands.push_back(
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AsmWriterOperand(
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"O.PadToColumn(TAI->getOperandColumn(OperandColumn++));\n",
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AsmWriterOperand::isLiteralStatementOperand));
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ReadingWhitespace = false;
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++GroupLevel;
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assert(GroupLevel < MAX_GROUP_NESTING_LEVEL
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&& "Exceeded maximum operand group nesting level");
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GroupDelim[GroupLevel] = AsmString[LastEmitted];
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AddLiteralString(std::string(1, AsmString[LastEmitted]));
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break;
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case ')': // Fallthrough
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case ']':
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if (InWhitespace() && !InGroup())
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Operands.push_back(
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AsmWriterOperand(
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"O.PadToColumn(TAI->getOperandColumn(OperandColumn++));\n",
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AsmWriterOperand::isLiteralStatementOperand));
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ReadingWhitespace = false;
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if (AsmString[LastEmitted] == ')')
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assert(GroupDelim[GroupLevel] == '(' && "Mismatched delimeters");
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else
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assert(GroupDelim[GroupLevel] == '[' && "Mismatched delimeters");
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--GroupLevel;
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assert(GroupLevel > -2 && "Too many end delimeters!");
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AddLiteralString(std::string(1, AsmString[LastEmitted]));
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break;
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default:
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if (AsmString[LastEmitted] != ' ' &&
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AsmString[LastEmitted] != '\t') {
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if (!InGroup() && InWhitespace())
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Operands.push_back(
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AsmWriterOperand(
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"O.PadToColumn(TAI->getOperandColumn(OperandColumn++));\n",
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AsmWriterOperand::isLiteralStatementOperand));
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ReadingWhitespace = false;
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}
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else
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if (!InGroup())
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ReadingWhitespace = true;
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AddLiteralString(std::string(1, AsmString[LastEmitted]));
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break;
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}
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} else {
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LastEmitted = DollarPos;
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}
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} else if (AsmString[DollarPos] == '\\') {
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if (DollarPos+1 != AsmString.size() &&
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(CurVariant == Variant || CurVariant == ~0U)) {
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if (AsmString[DollarPos+1] == 'n') {
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assert(!InGroup() && "Missing matching group delimeter");
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ReadingWhitespace = false;
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AddLiteralString("\\n");
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} else if (AsmString[DollarPos+1] == 't') {
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if (!InGroup()) {
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ReadingWhitespace = true;
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}
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AddLiteralString("\\t");
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} else if (std::string("${|}\\").find(AsmString[DollarPos+1])
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!= std::string::npos) {
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if (InWhitespace() && !InGroup())
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Operands.push_back(
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AsmWriterOperand(
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"O.PadToColumn(TAI->getOperandColumn(OperandColumn++));\n",
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AsmWriterOperand::isLiteralStatementOperand));
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ReadingWhitespace = false;
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if (AsmString[DollarPos+1] == '{') {
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++GroupLevel;
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assert(GroupLevel < MAX_GROUP_NESTING_LEVEL
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&& "Exceeded maximum operand group nesting level");
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GroupDelim[GroupLevel] = AsmString[DollarPos+1];
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} else if (AsmString[DollarPos+1] == '}') {
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assert(GroupDelim[GroupLevel] == '{' && "Mismatched delimeters");
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--GroupLevel;
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assert(GroupLevel > -2 && "Too many end delimeters!");
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}
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AddLiteralString(std::string(1, AsmString[DollarPos+1]));
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} else {
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throw "Non-supported escaped character found in instruction '" +
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CGI.TheDef->getName() + "'!";
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}
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LastEmitted = DollarPos+2;
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continue;
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}
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} else if (AsmString[DollarPos] == '{') {
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if (CurVariant != ~0U)
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throw "Nested variants found for instruction '" +
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CGI.TheDef->getName() + "'!";
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LastEmitted = DollarPos+1;
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CurVariant = 0; // We are now inside of the variant!
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} else if (AsmString[DollarPos] == '|') {
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if (CurVariant == ~0U)
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throw "'|' character found outside of a variant in instruction '"
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+ CGI.TheDef->getName() + "'!";
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++CurVariant;
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++LastEmitted;
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} else if (AsmString[DollarPos] == '}') {
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if (CurVariant == ~0U)
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throw "'}' character found outside of a variant in instruction '"
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+ CGI.TheDef->getName() + "'!";
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++LastEmitted;
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CurVariant = ~0U;
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} else if (DollarPos+1 != AsmString.size() &&
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AsmString[DollarPos+1] == '$') {
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if (CurVariant == Variant || CurVariant == ~0U) {
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if (InWhitespace() && !InGroup())
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Operands.push_back(
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AsmWriterOperand(
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"O.PadToColumn(TAI->getOperandColumn(OperandColumn++));\n",
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AsmWriterOperand::isLiteralStatementOperand));
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ReadingWhitespace = false;
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AddLiteralString("$"); // "$$" -> $
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}
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LastEmitted = DollarPos+2;
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} else {
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if (InWhitespace() && !InGroup())
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Operands.push_back(
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AsmWriterOperand(
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"O.PadToColumn(TAI->getOperandColumn(OperandColumn++));\n",
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AsmWriterOperand::isLiteralStatementOperand));
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ReadingWhitespace = false;
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// Get the name of the variable.
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std::string::size_type VarEnd = DollarPos+1;
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// handle ${foo}bar as $foo by detecting whether the character following
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// the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
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// so the variable name does not contain the leading curly brace.
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bool hasCurlyBraces = false;
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if (VarEnd < AsmString.size() && '{' == AsmString[VarEnd]) {
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hasCurlyBraces = true;
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++DollarPos;
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++VarEnd;
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}
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while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
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++VarEnd;
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std::string VarName(AsmString.begin()+DollarPos+1,
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AsmString.begin()+VarEnd);
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// Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
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// into printOperand. Also support ${:feature}, which is passed into
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// PrintSpecial.
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std::string Modifier;
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// In order to avoid starting the next string at the terminating curly
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// brace, advance the end position past it if we found an opening curly
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// brace.
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if (hasCurlyBraces) {
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if (VarEnd >= AsmString.size())
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throw "Reached end of string before terminating curly brace in '"
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+ CGI.TheDef->getName() + "'";
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// Look for a modifier string.
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if (AsmString[VarEnd] == ':') {
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++VarEnd;
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if (VarEnd >= AsmString.size())
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throw "Reached end of string before terminating curly brace in '"
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+ CGI.TheDef->getName() + "'";
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unsigned ModifierStart = VarEnd;
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while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
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++VarEnd;
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Modifier = std::string(AsmString.begin()+ModifierStart,
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AsmString.begin()+VarEnd);
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if (Modifier.empty())
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throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
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}
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if (AsmString[VarEnd] != '}')
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throw "Variable name beginning with '{' did not end with '}' in '"
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+ CGI.TheDef->getName() + "'";
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++VarEnd;
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}
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if (VarName.empty() && Modifier.empty())
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throw "Stray '$' in '" + CGI.TheDef->getName() +
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"' asm string, maybe you want $$?";
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if (VarName.empty()) {
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// Just a modifier, pass this into PrintSpecial.
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Operands.push_back(AsmWriterOperand("PrintSpecial", ~0U, Modifier));
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} else {
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// Otherwise, normal operand.
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unsigned OpNo = CGI.getOperandNamed(VarName);
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CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
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if (CurVariant == Variant || CurVariant == ~0U) {
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unsigned MIOp = OpInfo.MIOperandNo;
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Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,
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Modifier));
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}
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}
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LastEmitted = VarEnd;
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}
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}
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Operands.push_back(
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AsmWriterOperand("EmitComments(*MI);\n",
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AsmWriterOperand::isLiteralStatementOperand));
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AddLiteralString("\\n");
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}
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/// MatchesAllButOneOp - If this instruction is exactly identical to the
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/// specified instruction except for one differing operand, return the differing
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/// operand number. If more than one operand mismatches, return ~1, otherwise
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/// if the instructions are identical return ~0.
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unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
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if (Operands.size() != Other.Operands.size()) return ~1;
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unsigned MismatchOperand = ~0U;
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (Operands[i] != Other.Operands[i]) {
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if (MismatchOperand != ~0U) // Already have one mismatch?
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return ~1U;
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else
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MismatchOperand = i;
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}
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}
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return MismatchOperand;
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}
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static void PrintCases(std::vector<std::pair<std::string,
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AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
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O << " case " << OpsToPrint.back().first << ": ";
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AsmWriterOperand TheOp = OpsToPrint.back().second;
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OpsToPrint.pop_back();
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// Check to see if any other operands are identical in this list, and if so,
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// emit a case label for them.
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for (unsigned i = OpsToPrint.size(); i != 0; --i)
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if (OpsToPrint[i-1].second == TheOp) {
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O << "\n case " << OpsToPrint[i-1].first << ": ";
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OpsToPrint.erase(OpsToPrint.begin()+i-1);
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}
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// Finally, emit the code.
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O << TheOp.getCode();
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O << "break;\n";
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}
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/// EmitInstructions - Emit the last instruction in the vector and any other
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/// instructions that are suitably similar to it.
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static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
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raw_ostream &O) {
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AsmWriterInst FirstInst = Insts.back();
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Insts.pop_back();
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std::vector<AsmWriterInst> SimilarInsts;
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unsigned DifferingOperand = ~0;
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for (unsigned i = Insts.size(); i != 0; --i) {
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unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
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if (DiffOp != ~1U) {
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if (DifferingOperand == ~0U) // First match!
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DifferingOperand = DiffOp;
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// If this differs in the same operand as the rest of the instructions in
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|
// this class, move it to the SimilarInsts list.
|
|
if (DifferingOperand == DiffOp || DiffOp == ~0U) {
|
|
SimilarInsts.push_back(Insts[i-1]);
|
|
Insts.erase(Insts.begin()+i-1);
|
|
}
|
|
}
|
|
}
|
|
|
|
O << " case " << FirstInst.CGI->Namespace << "::"
|
|
<< FirstInst.CGI->TheDef->getName() << ":\n";
|
|
for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
|
|
O << " case " << SimilarInsts[i].CGI->Namespace << "::"
|
|
<< SimilarInsts[i].CGI->TheDef->getName() << ":\n";
|
|
for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
|
|
if (i != DifferingOperand) {
|
|
// If the operand is the same for all instructions, just print it.
|
|
O << " " << FirstInst.Operands[i].getCode();
|
|
} else {
|
|
// If this is the operand that varies between all of the instructions,
|
|
// emit a switch for just this operand now.
|
|
O << " switch (MI->getOpcode()) {\n";
|
|
std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
|
|
OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
|
|
FirstInst.CGI->TheDef->getName(),
|
|
FirstInst.Operands[i]));
|
|
|
|
for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
|
|
AsmWriterInst &AWI = SimilarInsts[si];
|
|
OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
|
|
AWI.CGI->TheDef->getName(),
|
|
AWI.Operands[i]));
|
|
}
|
|
std::reverse(OpsToPrint.begin(), OpsToPrint.end());
|
|
while (!OpsToPrint.empty())
|
|
PrintCases(OpsToPrint, O);
|
|
O << " }";
|
|
}
|
|
O << "\n";
|
|
}
|
|
O << " break;\n";
|
|
}
|
|
|
|
void AsmWriterEmitter::
|
|
FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
|
|
std::vector<unsigned> &InstIdxs,
|
|
std::vector<unsigned> &InstOpsUsed) const {
|
|
InstIdxs.assign(NumberedInstructions.size(), ~0U);
|
|
|
|
// This vector parallels UniqueOperandCommands, keeping track of which
|
|
// instructions each case are used for. It is a comma separated string of
|
|
// enums.
|
|
std::vector<std::string> InstrsForCase;
|
|
InstrsForCase.resize(UniqueOperandCommands.size());
|
|
InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
|
|
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
const AsmWriterInst *Inst = getAsmWriterInstByID(i);
|
|
if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc.
|
|
|
|
std::string Command;
|
|
if (Inst->Operands.empty())
|
|
continue; // Instruction already done.
|
|
|
|
Command = " " + Inst->Operands[0].getCode() + "\n";
|
|
|
|
// If this is the last operand, emit a return.
|
|
if (Inst->Operands.size() == 1) {
|
|
Command += " return true;\n";
|
|
}
|
|
|
|
// Check to see if we already have 'Command' in UniqueOperandCommands.
|
|
// If not, add it.
|
|
bool FoundIt = false;
|
|
for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
|
|
if (UniqueOperandCommands[idx] == Command) {
|
|
InstIdxs[i] = idx;
|
|
InstrsForCase[idx] += ", ";
|
|
InstrsForCase[idx] += Inst->CGI->TheDef->getName();
|
|
FoundIt = true;
|
|
break;
|
|
}
|
|
if (!FoundIt) {
|
|
InstIdxs[i] = UniqueOperandCommands.size();
|
|
UniqueOperandCommands.push_back(Command);
|
|
InstrsForCase.push_back(Inst->CGI->TheDef->getName());
|
|
|
|
// This command matches one operand so far.
|
|
InstOpsUsed.push_back(1);
|
|
}
|
|
}
|
|
|
|
// For each entry of UniqueOperandCommands, there is a set of instructions
|
|
// that uses it. If the next command of all instructions in the set are
|
|
// identical, fold it into the command.
|
|
for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
|
|
CommandIdx != e; ++CommandIdx) {
|
|
|
|
for (unsigned Op = 1; ; ++Op) {
|
|
// Scan for the first instruction in the set.
|
|
std::vector<unsigned>::iterator NIT =
|
|
std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
|
|
if (NIT == InstIdxs.end()) break; // No commonality.
|
|
|
|
// If this instruction has no more operands, we isn't anything to merge
|
|
// into this command.
|
|
const AsmWriterInst *FirstInst =
|
|
getAsmWriterInstByID(NIT-InstIdxs.begin());
|
|
if (!FirstInst || FirstInst->Operands.size() == Op)
|
|
break;
|
|
|
|
// Otherwise, scan to see if all of the other instructions in this command
|
|
// set share the operand.
|
|
bool AllSame = true;
|
|
// Keep track of the maximum, number of operands or any
|
|
// instruction we see in the group.
|
|
size_t MaxSize = FirstInst->Operands.size();
|
|
|
|
for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
|
|
NIT != InstIdxs.end();
|
|
NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
|
|
// Okay, found another instruction in this command set. If the operand
|
|
// matches, we're ok, otherwise bail out.
|
|
const AsmWriterInst *OtherInst =
|
|
getAsmWriterInstByID(NIT-InstIdxs.begin());
|
|
|
|
if (OtherInst &&
|
|
OtherInst->Operands.size() > FirstInst->Operands.size())
|
|
MaxSize = std::max(MaxSize, OtherInst->Operands.size());
|
|
|
|
if (!OtherInst || OtherInst->Operands.size() == Op ||
|
|
OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
|
|
AllSame = false;
|
|
break;
|
|
}
|
|
}
|
|
if (!AllSame) break;
|
|
|
|
// Okay, everything in this command set has the same next operand. Add it
|
|
// to UniqueOperandCommands and remember that it was consumed.
|
|
std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
|
|
|
|
// If this is the last operand, emit a return after the code.
|
|
if (FirstInst->Operands.size() == Op+1 &&
|
|
// Don't early-out too soon. Other instructions in this
|
|
// group may have more operands.
|
|
FirstInst->Operands.size() == MaxSize) {
|
|
Command += " return true;\n";
|
|
}
|
|
|
|
UniqueOperandCommands[CommandIdx] += Command;
|
|
InstOpsUsed[CommandIdx]++;
|
|
}
|
|
}
|
|
|
|
// Prepend some of the instructions each case is used for onto the case val.
|
|
for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
|
|
std::string Instrs = InstrsForCase[i];
|
|
if (Instrs.size() > 70) {
|
|
Instrs.erase(Instrs.begin()+70, Instrs.end());
|
|
Instrs += "...";
|
|
}
|
|
|
|
if (!Instrs.empty())
|
|
UniqueOperandCommands[i] = " // " + Instrs + "\n" +
|
|
UniqueOperandCommands[i];
|
|
}
|
|
}
|
|
|
|
|
|
|
|
void AsmWriterEmitter::run(raw_ostream &O) {
|
|
EmitSourceFileHeader("Assembly Writer Source Fragment", O);
|
|
|
|
CodeGenTarget Target;
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
|
unsigned Variant = AsmWriter->getValueAsInt("Variant");
|
|
|
|
O <<
|
|
"/// printInstruction - This method is automatically generated by tablegen\n"
|
|
"/// from the instruction set description. This method returns true if the\n"
|
|
"/// machine instruction was sufficiently described to print it, otherwise\n"
|
|
"/// it returns false.\n"
|
|
"bool " << Target.getName() << ClassName
|
|
<< "::printInstruction(const MachineInstr *MI) {\n";
|
|
|
|
std::vector<AsmWriterInst> Instructions;
|
|
|
|
for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
|
|
E = Target.inst_end(); I != E; ++I)
|
|
if (!I->second.AsmString.empty())
|
|
Instructions.push_back(AsmWriterInst(I->second, Variant));
|
|
|
|
// Get the instruction numbering.
|
|
Target.getInstructionsByEnumValue(NumberedInstructions);
|
|
|
|
// Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
|
|
// all machine instructions are necessarily being printed, so there may be
|
|
// target instructions not in this map.
|
|
for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
|
|
CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
|
|
|
|
// Build an aggregate string, and build a table of offsets into it.
|
|
std::map<std::string, unsigned> StringOffset;
|
|
std::string AggregateString;
|
|
AggregateString.push_back(0); // "\0"
|
|
AggregateString.push_back(0); // "\0"
|
|
|
|
/// OpcodeInfo - This encodes the index of the string to use for the first
|
|
/// chunk of the output as well as indices used for operand printing.
|
|
std::vector<unsigned> OpcodeInfo;
|
|
|
|
unsigned MaxStringIdx = 0;
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
|
|
unsigned Idx;
|
|
if (AWI == 0) {
|
|
// Something not handled by the asmwriter printer.
|
|
Idx = 0;
|
|
} else if (AWI->Operands[0].OperandType !=
|
|
AsmWriterOperand::isLiteralTextOperand ||
|
|
AWI->Operands[0].Str.empty()) {
|
|
// Something handled by the asmwriter printer, but with no leading string.
|
|
Idx = 1;
|
|
} else {
|
|
unsigned &Entry = StringOffset[AWI->Operands[0].Str];
|
|
if (Entry == 0) {
|
|
// Add the string to the aggregate if this is the first time found.
|
|
MaxStringIdx = Entry = AggregateString.size();
|
|
std::string Str = AWI->Operands[0].Str;
|
|
UnescapeString(Str);
|
|
AggregateString += Str;
|
|
AggregateString += '\0';
|
|
}
|
|
Idx = Entry;
|
|
|
|
// Nuke the string from the operand list. It is now handled!
|
|
AWI->Operands.erase(AWI->Operands.begin());
|
|
}
|
|
OpcodeInfo.push_back(Idx);
|
|
}
|
|
|
|
// Figure out how many bits we used for the string index.
|
|
unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+1);
|
|
|
|
// To reduce code size, we compactify common instructions into a few bits
|
|
// in the opcode-indexed table.
|
|
unsigned BitsLeft = 32-AsmStrBits;
|
|
|
|
std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
|
|
|
|
bool isFirst = true;
|
|
while (1) {
|
|
std::vector<std::string> UniqueOperandCommands;
|
|
|
|
// For the first operand check, add a default value for instructions with
|
|
// just opcode strings to use.
|
|
if (isFirst) {
|
|
UniqueOperandCommands.push_back(" return true;\n");
|
|
isFirst = false;
|
|
}
|
|
|
|
std::vector<unsigned> InstIdxs;
|
|
std::vector<unsigned> NumInstOpsHandled;
|
|
FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
|
|
NumInstOpsHandled);
|
|
|
|
// If we ran out of operands to print, we're done.
|
|
if (UniqueOperandCommands.empty()) break;
|
|
|
|
// Compute the number of bits we need to represent these cases, this is
|
|
// ceil(log2(numentries)).
|
|
unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
|
|
|
|
// If we don't have enough bits for this operand, don't include it.
|
|
if (NumBits > BitsLeft) {
|
|
DOUT << "Not enough bits to densely encode " << NumBits
|
|
<< " more bits\n";
|
|
break;
|
|
}
|
|
|
|
// Otherwise, we can include this in the initial lookup table. Add it in.
|
|
BitsLeft -= NumBits;
|
|
for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
|
|
if (InstIdxs[i] != ~0U)
|
|
OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
|
|
|
|
// Remove the info about this operand.
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
|
|
if (!Inst->Operands.empty()) {
|
|
unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
|
|
assert(NumOps <= Inst->Operands.size() &&
|
|
"Can't remove this many ops!");
|
|
Inst->Operands.erase(Inst->Operands.begin(),
|
|
Inst->Operands.begin()+NumOps);
|
|
}
|
|
}
|
|
|
|
// Remember the handlers for this set of operands.
|
|
TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
|
|
}
|
|
|
|
|
|
|
|
O<<" static const unsigned OpInfo[] = {\n";
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
O << " " << OpcodeInfo[i] << "U,\t// "
|
|
<< NumberedInstructions[i]->TheDef->getName() << "\n";
|
|
}
|
|
// Add a dummy entry so the array init doesn't end with a comma.
|
|
O << " 0U\n";
|
|
O << " };\n\n";
|
|
|
|
// Emit the string itself.
|
|
O << " const char *AsmStrs = \n \"";
|
|
unsigned CharsPrinted = 0;
|
|
EscapeString(AggregateString);
|
|
for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
|
|
if (CharsPrinted > 70) {
|
|
O << "\"\n \"";
|
|
CharsPrinted = 0;
|
|
}
|
|
O << AggregateString[i];
|
|
++CharsPrinted;
|
|
|
|
// Print escape sequences all together.
|
|
if (AggregateString[i] == '\\') {
|
|
assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
|
|
if (isdigit(AggregateString[i+1])) {
|
|
assert(isdigit(AggregateString[i+2]) && isdigit(AggregateString[i+3]) &&
|
|
"Expected 3 digit octal escape!");
|
|
O << AggregateString[++i];
|
|
O << AggregateString[++i];
|
|
O << AggregateString[++i];
|
|
CharsPrinted += 3;
|
|
} else {
|
|
O << AggregateString[++i];
|
|
++CharsPrinted;
|
|
}
|
|
}
|
|
}
|
|
O << "\";\n\n";
|
|
|
|
O << " processDebugLoc(MI->getDebugLoc());\n\n";
|
|
|
|
O << "\n#ifndef NO_ASM_WRITER_BOILERPLATE\n";
|
|
|
|
O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n"
|
|
<< " O << \"\\t\";\n"
|
|
<< " printInlineAsm(MI);\n"
|
|
<< " return true;\n"
|
|
<< " } else if (MI->isLabel()) {\n"
|
|
<< " printLabel(MI);\n"
|
|
<< " return true;\n"
|
|
<< " } else if (MI->getOpcode() == TargetInstrInfo::DECLARE) {\n"
|
|
<< " printDeclare(MI);\n"
|
|
<< " return true;\n"
|
|
<< " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n"
|
|
<< " printImplicitDef(MI);\n"
|
|
<< " return true;\n"
|
|
<< " }\n\n";
|
|
|
|
O << "\n#endif\n";
|
|
|
|
O << " O << \"\\t\";\n\n";
|
|
|
|
O << " // Emit the opcode for the instruction.\n"
|
|
<< " unsigned Bits = OpInfo[MI->getOpcode()];\n"
|
|
<< " if (Bits == 0) return false;\n\n";
|
|
|
|
O << " unsigned OperandColumn = 1;\n\n"
|
|
<< " if (TAI->getOperandColumn(1) > 0) {\n"
|
|
<< " // Don't emit trailing whitespace, let the column padding do it. This\n"
|
|
<< " // guarantees that a stray long opcode + tab won't upset the alignment.\n"
|
|
<< " unsigned OpLength = std::strlen(AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << "));\n"
|
|
<< " if (OpLength > 0 &&\n"
|
|
<< " ((AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << "))[OpLength-1] == ' ' ||\n"
|
|
<< " (AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << "))[OpLength-1] == '\\t')) {\n"
|
|
<< " do {\n"
|
|
<< " --OpLength;\n"
|
|
<< " } while ((AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << "))[OpLength-1] == ' ' ||\n"
|
|
<< " (AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << "))[OpLength-1] == '\\t');\n"
|
|
<< " for (unsigned Idx = 0; Idx < OpLength; ++Idx)\n"
|
|
<< " O << (AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << "))[Idx];\n"
|
|
<< " O.PadToColumn(TAI->getOperandColumn(OperandColumn++), 1);\n"
|
|
<< " }\n"
|
|
<< " } else {\n"
|
|
<< " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n"
|
|
<< " }\n\n";
|
|
|
|
|
|
// Output the table driven operand information.
|
|
BitsLeft = 32-AsmStrBits;
|
|
for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
|
|
std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
|
|
|
|
// Compute the number of bits we need to represent these cases, this is
|
|
// ceil(log2(numentries)).
|
|
unsigned NumBits = Log2_32_Ceil(Commands.size());
|
|
assert(NumBits <= BitsLeft && "consistency error");
|
|
|
|
// Emit code to extract this field from Bits.
|
|
BitsLeft -= NumBits;
|
|
|
|
O << "\n // Fragment " << i << " encoded into " << NumBits
|
|
<< " bits for " << Commands.size() << " unique commands.\n";
|
|
|
|
if (Commands.size() == 2) {
|
|
// Emit two possibilitys with if/else.
|
|
O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
|
|
<< ((1 << NumBits)-1) << ") {\n"
|
|
<< Commands[1]
|
|
<< " } else {\n"
|
|
<< Commands[0]
|
|
<< " }\n\n";
|
|
} else {
|
|
O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
|
|
<< ((1 << NumBits)-1) << ") {\n"
|
|
<< " default: // unreachable.\n";
|
|
|
|
// Print out all the cases.
|
|
for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
|
|
O << " case " << i << ":\n";
|
|
O << Commands[i];
|
|
O << " break;\n";
|
|
}
|
|
O << " }\n\n";
|
|
}
|
|
}
|
|
|
|
// Okay, delete instructions with no operand info left.
|
|
for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
|
|
// Entire instruction has been emitted?
|
|
AsmWriterInst &Inst = Instructions[i];
|
|
if (Inst.Operands.empty()) {
|
|
Instructions.erase(Instructions.begin()+i);
|
|
--i; --e;
|
|
}
|
|
}
|
|
|
|
|
|
// Because this is a vector, we want to emit from the end. Reverse all of the
|
|
// elements in the vector.
|
|
std::reverse(Instructions.begin(), Instructions.end());
|
|
|
|
if (!Instructions.empty()) {
|
|
// Find the opcode # of inline asm.
|
|
O << " switch (MI->getOpcode()) {\n";
|
|
while (!Instructions.empty())
|
|
EmitInstructions(Instructions, O);
|
|
|
|
O << " }\n";
|
|
O << " return true;\n";
|
|
}
|
|
|
|
O << " return true;\n";
|
|
O << "}\n";
|
|
}
|