mirror of
https://github.com/c64scene-ar/llvm-6502.git
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65f2e7887a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78562 91177308-0d34-0410-b5e6-96231b3b80d8
397 lines
14 KiB
C++
397 lines
14 KiB
C++
//===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "t2-reduce-size"
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#include "ARM.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMBaseInstrInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
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STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
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static cl::opt<int> ReduceLimit("t2-reduce-limit", cl::init(-1), cl::Hidden);
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namespace {
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/// ReduceTable - A static table with information on mapping from wide
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/// opcodes to narrow
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struct ReduceEntry {
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unsigned WideOpc; // Wide opcode
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unsigned NarrowOpc1; // Narrow opcode to transform to
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unsigned NarrowOpc2; // Narrow opcode when it's two-address
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uint8_t Imm1Limit; // Limit of immediate field (bits)
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uint8_t Imm2Limit; // Limit of immediate field when it's two-address
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unsigned LowRegs1 : 1; // Only possible if low-registers are used
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unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
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unsigned PredCC1 : 1; // 0 - If predicated, cc is on and vice versa.
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// 1 - No cc field.
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unsigned PredCC2 : 1;
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unsigned Special : 1; // Needs to be dealt with specially
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};
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static const ReduceEntry ReduceTable[] = {
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// Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, S
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{ ARM::t2ADCrr, ARM::tADC, 0, 0, 0, 1, 0, 0,0, 0 },
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// FIXME: t2ADDS variants.
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{ ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0 },
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{ ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0 },
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{ ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 0 },
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{ ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 1,0, 0 },
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{ ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 1,0, 0 },
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{ ARM::t2CMPzri,ARM::tCMPzi8, 0, 8, 0, 1, 0, 1,0, 0 },
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{ ARM::t2CMPzrr,ARM::tCMPzhir,0, 0, 0, 0, 0, 1,0, 0 },
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{ ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 0 },
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{ ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 0 },
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{ ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 },
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// FIXME: Do we need the 16-bit 'S' variant?
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// FIXME: t2MOVcc
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{ ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0 },
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{ ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 0 },
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{ ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 0 },
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// FIXME: T2RSBri immediate must be zero. Also need entry for T2RSBS
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//{ ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0 },
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{ ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0 },
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{ ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0 },
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{ ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0 }
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};
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class VISIBILITY_HIDDEN Thumb2SizeReduce : public MachineFunctionPass {
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public:
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static char ID;
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Thumb2SizeReduce();
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const TargetInstrInfo *TII;
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "Thumb2 instruction size reduction pass";
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}
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private:
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/// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
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DenseMap<unsigned, unsigned> ReduceOpcodeMap;
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/// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
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/// instruction.
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bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR);
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/// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
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/// non-two-address instruction.
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bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR);
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/// ReduceMBB - Reduce width of instructions in the specified basic block.
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bool ReduceMBB(MachineBasicBlock &MBB);
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};
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char Thumb2SizeReduce::ID = 0;
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}
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Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(&ID) {
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for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
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unsigned FromOpc = ReduceTable[i].WideOpc;
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if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
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assert(false && "Duplicated entries?");
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}
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}
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static bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
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bool is2Addr, ARMCC::CondCodes Pred,
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bool LiveCPSR, bool &HasCC, bool &CCDead) {
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if ((is2Addr && Entry.PredCC2 == 0) ||
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(!is2Addr && Entry.PredCC1 == 0)) {
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if (Pred == ARMCC::AL) {
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// Not predicated, must set CPSR.
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if (!HasCC) {
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// Original instruction was not setting CPSR, but CPSR is not
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// currently live anyway. It's ok to set it. The CPSR def is
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// dead though.
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if (!LiveCPSR) {
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HasCC = true;
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CCDead = true;
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return true;
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}
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return false;
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}
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} else {
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// Predicated, must not set CPSR.
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if (HasCC)
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return false;
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}
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} else {
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// 16-bit instruction does not set CPSR.
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if (HasCC)
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return false;
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}
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return true;
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}
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bool
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Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR) {
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const TargetInstrDesc &TID = MI->getDesc();
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unsigned Reg0 = MI->getOperand(0).getReg();
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unsigned Reg1 = MI->getOperand(1).getReg();
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if (Reg0 != Reg1)
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return false;
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if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
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return false;
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if (Entry.Imm2Limit) {
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unsigned Imm = MI->getOperand(2).getImm();
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unsigned Limit = (1 << Entry.Imm2Limit) - 1;
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if (Imm > Limit)
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return false;
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} else {
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unsigned Reg2 = MI->getOperand(2).getReg();
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if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
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return false;
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}
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// Check if it's possible / necessary to transfer the predicate.
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const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc2);
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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bool SkipPred = false;
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if (Pred != ARMCC::AL) {
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if (!NewTID.isPredicable())
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// Can't transfer predicate, fail.
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return false;
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} else {
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SkipPred = !NewTID.isPredicable();
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}
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bool HasCC = false;
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bool CCDead = false;
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if (TID.hasOptionalDef()) {
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unsigned NumOps = TID.getNumOperands();
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HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
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if (HasCC && MI->getOperand(NumOps-1).isDead())
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CCDead = true;
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}
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if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
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return false;
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// Add the 16-bit instruction.
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DebugLoc dl = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Entry.NarrowOpc2));
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MIB.addOperand(MI->getOperand(0));
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if (HasCC)
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AddDefaultT1CC(MIB, CCDead);
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// Transfer the rest of operands.
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unsigned NumOps = TID.getNumOperands();
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
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if (i < NumOps && TID.OpInfo[i].isOptionalDef())
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continue;
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if (SkipPred && TID.OpInfo[i].isPredicate())
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continue;
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MIB.addOperand(MI->getOperand(i));
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}
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DOUT << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB;
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MBB.erase(MI);
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++Num2Addrs;
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return true;
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}
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bool
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Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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const ReduceEntry &Entry,
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bool LiveCPSR) {
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unsigned Limit = ~0U;
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if (Entry.Imm1Limit)
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Limit = (1 << Entry.Imm1Limit) - 1;
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const TargetInstrDesc &TID = MI->getDesc();
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for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
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if (TID.OpInfo[i].isPredicate())
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continue;
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg()) {
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unsigned Reg = MO.getReg();
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if (!Reg || Reg == ARM::CPSR)
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continue;
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if (Entry.LowRegs1 && !isARMLowRegister(Reg))
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return false;
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} else if (MO.isImm()) {
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if (MO.getImm() > Limit)
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return false;
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}
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}
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// Check if it's possible / necessary to transfer the predicate.
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const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc1);
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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bool SkipPred = false;
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if (Pred != ARMCC::AL) {
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if (!NewTID.isPredicable())
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// Can't transfer predicate, fail.
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return false;
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} else {
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SkipPred = !NewTID.isPredicable();
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}
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bool HasCC = false;
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bool CCDead = false;
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if (TID.hasOptionalDef()) {
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unsigned NumOps = TID.getNumOperands();
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HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
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if (HasCC && MI->getOperand(NumOps-1).isDead())
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CCDead = true;
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}
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if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
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return false;
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// Add the 16-bit instruction.
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DebugLoc dl = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Entry.NarrowOpc1));
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MIB.addOperand(MI->getOperand(0));
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if (HasCC)
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AddDefaultT1CC(MIB, CCDead);
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// Transfer the rest of operands.
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unsigned NumOps = TID.getNumOperands();
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
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if (i < NumOps && TID.OpInfo[i].isOptionalDef())
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continue;
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if (SkipPred && TID.OpInfo[i].isPredicate())
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continue;
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MIB.addOperand(MI->getOperand(i));
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}
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DOUT << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB;
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MBB.erase(MI);
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++NumNarrows;
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return true;
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}
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static bool UpdateCPSRLiveness(MachineInstr &MI, bool LiveCPSR) {
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bool HasDef = false;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg() || MO.isUndef())
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continue;
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if (MO.getReg() != ARM::CPSR)
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continue;
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if (MO.isDef()) {
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if (!MO.isDead())
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HasDef = true;
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continue;
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}
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assert(LiveCPSR && "CPSR liveness tracking is wrong!");
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if (MO.isKill()) {
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LiveCPSR = false;
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break;
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}
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}
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return HasDef || LiveCPSR;
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}
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bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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bool LiveCPSR = false;
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// Yes, CPSR could be livein.
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for (MachineBasicBlock::const_livein_iterator I = MBB.livein_begin(),
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E = MBB.livein_end(); I != E; ++I) {
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if (*I == ARM::CPSR) {
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LiveCPSR = true;
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break;
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}
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}
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MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
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MachineBasicBlock::iterator NextMII;
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for (; MII != E; MII = NextMII) {
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NextMII = next(MII);
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MachineInstr *MI = &*MII;
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unsigned Opcode = MI->getOpcode();
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DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
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if (OPI != ReduceOpcodeMap.end()) {
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const ReduceEntry &Entry = ReduceTable[OPI->second];
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// Ignore "special" cases for now.
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if (Entry.Special)
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goto ProcessNext;
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// Try to transform to a 16-bit two-address instruction.
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if (Entry.NarrowOpc2 && ReduceTo2Addr(MBB, MI, Entry, LiveCPSR)) {
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Modified = true;
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MachineBasicBlock::iterator I = prior(NextMII);
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MI = &*I;
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goto ProcessNext;
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}
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// Try to transform ro a 16-bit non-two-address instruction.
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if (Entry.NarrowOpc1 && ReduceToNarrow(MBB, MI, Entry, LiveCPSR))
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Modified = true;
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}
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ProcessNext:
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LiveCPSR = UpdateCPSRLiveness(*MI, LiveCPSR);
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if (ReduceLimit != -1 && ((int)(NumNarrows + Num2Addrs) > ReduceLimit))
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break;
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}
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return Modified;
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}
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bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
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const TargetMachine &TM = MF.getTarget();
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TII = TM.getInstrInfo();
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bool Modified = false;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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Modified |= ReduceMBB(*I);
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return Modified;
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}
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/// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
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/// reduction pass.
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FunctionPass *llvm::createThumb2SizeReductionPass() {
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return new Thumb2SizeReduce();
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}
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