mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-22 07:32:48 +00:00
5fa8186b8d
- lit tests verify that each line of input LLVM IR gets a !dbg node and a corresponding entry of metadata that contains the line number - unit tests verify that DebugIR works as advertised in the interface - refactored some useful IR generation functionality from the MCJIT unit tests so it can be reused git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185212 91177308-0d34-0410-b5e6-96231b3b80d8
94 lines
6.0 KiB
LLVM
94 lines
6.0 KiB
LLVM
; ModuleID = 'vector.cpp'
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-pc-linux-gnu"
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; Function Attrs: noinline nounwind uwtable
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define <4 x float> @_Z3fooDv2_fS_(double %a.coerce, double %b.coerce) #0 {
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%1 = alloca <2 x float>, align 8 ; CHECK: !dbg
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%2 = alloca <2 x float>, align 8 ; CHECK-NEXT: !dbg
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%3 = alloca <2 x float>, align 8 ; CHECK-NEXT: !dbg
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%4 = alloca <2 x float>, align 8 ; CHECK-NEXT: !dbg
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%c = alloca <4 x float>, align 16 ; CHECK-NEXT: !dbg
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%5 = bitcast <2 x float>* %1 to double* ; CHECK-NEXT: !dbg
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store double %a.coerce, double* %5, align 1 ; CHECK-NEXT: !dbg
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%a = load <2 x float>* %1, align 8 ; CHECK-NEXT: !dbg
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store <2 x float> %a, <2 x float>* %2, align 8 ; CHECK-NEXT: !dbg
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%6 = bitcast <2 x float>* %3 to double* ; CHECK-NEXT: !dbg
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store double %b.coerce, double* %6, align 1 ; CHECK-NEXT: !dbg
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%b = load <2 x float>* %3, align 8 ; CHECK-NEXT: !dbg
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store <2 x float> %b, <2 x float>* %4, align 8 ; CHECK-NEXT: !dbg
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%7 = load <2 x float>* %2, align 8 ; CHECK-NEXT: !dbg
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%8 = load <4 x float>* %c, align 16 ; CHECK-NEXT: !dbg
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%9 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: !dbg
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%10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> <i32 4, i32 1, i32 5, i32 3> ; CHECK-NEXT: !dbg
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store <4 x float> %10, <4 x float>* %c, align 16 ; CHECK-NEXT: !dbg
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%11 = load <2 x float>* %4, align 8 ; CHECK-NEXT: !dbg
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%12 = load <4 x float>* %c, align 16 ; CHECK-NEXT: !dbg
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%13 = shufflevector <2 x float> %11, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: !dbg
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%14 = shufflevector <4 x float> %12, <4 x float> %13, <4 x i32> <i32 0, i32 4, i32 2, i32 5> ; CHECK-NEXT: !dbg
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store <4 x float> %14, <4 x float>* %c, align 16 ; CHECK-NEXT: !dbg
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%15 = load <4 x float>* %c, align 16 ; CHECK-NEXT: !dbg
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ret <4 x float> %15 ; CHECK-NEXT: !dbg
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}
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; Function Attrs: nounwind uwtable
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define i32 @main() #1 {
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%1 = alloca i32, align 4 ; CHECK: !dbg
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%a = alloca <2 x float>, align 8 ; CHECK-NEXT: !dbg
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%b = alloca <2 x float>, align 8 ; CHECK-NEXT: !dbg
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%x = alloca <4 x float>, align 16 ; CHECK-NEXT: !dbg
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%2 = alloca <2 x float>, align 8 ; CHECK-NEXT: !dbg
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%3 = alloca <2 x float>, align 8 ; CHECK-NEXT: !dbg
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store i32 0, i32* %1 ; CHECK-NEXT: !dbg
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store <2 x float> <float 1.000000e+00, float 2.000000e+00>, <2 x float>* %a, align 8 ; CHECK-NEXT: !dbg
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store <2 x float> <float 1.000000e+00, float 2.000000e+00>, <2 x float>* %b, align 8 ; CHECK-NEXT: !dbg
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%4 = load <2 x float>* %a, align 8 ; CHECK-NEXT: !dbg
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%5 = load <2 x float>* %b, align 8 ; CHECK-NEXT: !dbg
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store <2 x float> %4, <2 x float>* %2, align 8 ; CHECK-NEXT: !dbg
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%6 = bitcast <2 x float>* %2 to double* ; CHECK-NEXT: !dbg
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%7 = load double* %6, align 1 ; CHECK-NEXT: !dbg
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store <2 x float> %5, <2 x float>* %3, align 8 ; CHECK-NEXT: !dbg
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%8 = bitcast <2 x float>* %3 to double* ; CHECK-NEXT: !dbg
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%9 = load double* %8, align 1 ; CHECK-NEXT: !dbg
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%10 = call <4 x float> @_Z3fooDv2_fS_(double %7, double %9) ; CHECK-NEXT: !dbg
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store <4 x float> %10, <4 x float>* %x, align 16 ; CHECK-NEXT: !dbg
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%11 = load <4 x float>* %x, align 16 ; CHECK-NEXT: !dbg
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%12 = extractelement <4 x float> %11, i32 0 ; CHECK-NEXT: !dbg
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%13 = load <4 x float>* %x, align 16 ; CHECK-NEXT: !dbg
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%14 = extractelement <4 x float> %13, i32 1 ; CHECK-NEXT: !dbg
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%15 = fadd float %12, %14 ; CHECK-NEXT: !dbg
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%16 = load <4 x float>* %x, align 16 ; CHECK-NEXT: !dbg
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%17 = extractelement <4 x float> %16, i32 2 ; CHECK-NEXT: !dbg
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%18 = fadd float %15, %17 ; CHECK-NEXT: !dbg
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%19 = load <4 x float>* %x, align 16 ; CHECK-NEXT: !dbg
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%20 = extractelement <4 x float> %19, i32 3 ; CHECK-NEXT: !dbg
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%21 = fadd float %18, %20 ; CHECK-NEXT: !dbg
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%22 = fptosi float %21 to i32 ; CHECK-NEXT: !dbg
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ret i32 %22 ; CHECK-NEXT: !dbg
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}
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attributes #0 = { noinline nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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; CHECK: = metadata !{i32 13,
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; CHECK-NEXT: = metadata !{i32 14,
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; CHECK-NEXT: = metadata !{i32 15,
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; CHECK-NEXT: = metadata !{i32 16,
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; CHECK-NEXT: = metadata !{i32 17,
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; CHECK-NEXT: = metadata !{i32 18,
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; CHECK-NEXT: = metadata !{i32 19,
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; CHECK-NEXT: = metadata !{i32 20,
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; CHECK-NEXT: = metadata !{i32 21,
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; CHECK-NEXT: = metadata !{i32 22,
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; CHECK-NEXT: = metadata !{i32 23,
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; CHECK-NEXT: = metadata !{i32 24,
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; CHECK-NEXT: = metadata !{i32 25,
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; CHECK-NEXT: = metadata !{i32 26,
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; CHECK-NEXT: = metadata !{i32 27,
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; CHECK-NEXT: = metadata !{i32 28,
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; CHECK-NEXT: = metadata !{i32 29,
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; CHECK-NEXT: = metadata !{i32 30,
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; CHECK-NEXT: = metadata !{i32 31,
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; RUN: opt %s -debug-ir -S | FileCheck %s
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