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https://github.com/c64scene-ar/llvm-6502.git
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0f1bcedf5a
The order in which operands appear in the encoded instruction is different to order in which they appear in assembly. This changes the XCore backend to use the instruction encoding order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173493 91177308-0d34-0410-b5e6-96231b3b80d8
297 lines
11 KiB
C++
297 lines
11 KiB
C++
//===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the XCore target.
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//
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//===----------------------------------------------------------------------===//
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#include "XCore.h"
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#include "XCoreTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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/// XCoreDAGToDAGISel - XCore specific code to select XCore machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class XCoreDAGToDAGISel : public SelectionDAGISel {
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const XCoreTargetLowering &Lowering;
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const XCoreSubtarget &Subtarget;
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public:
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XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel),
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Lowering(*TM.getTargetLowering()),
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Subtarget(*TM.getSubtargetImpl()) { }
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SDNode *Select(SDNode *N);
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SDNode *SelectBRIND(SDNode *N);
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDValue getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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inline bool immMskBitp(SDNode *inN) const {
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ConstantSDNode *N = cast<ConstantSDNode>(inN);
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uint32_t value = (uint32_t)N->getZExtValue();
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if (!isMask_32(value)) {
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return false;
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}
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int msksize = 32 - CountLeadingZeros_32(value);
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return (msksize >= 1 && msksize <= 8) ||
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msksize == 16 || msksize == 24 || msksize == 32;
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}
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// Complex Pattern Selectors.
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bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRdpii(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRcpii(SDValue Addr, SDValue &Base, SDValue &Offset);
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virtual const char *getPassName() const {
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return "XCore DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "XCoreGenDAGISel.inc"
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};
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} // end anonymous namespace
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/// createXCoreISelDag - This pass converts a legalized DAG into a
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/// XCore-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new XCoreDAGToDAGISel(TM, OptLevel);
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}
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bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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FrameIndexSDNode *FIN = 0;
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if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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ConstantSDNode *CN = 0;
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if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
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&& (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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&& (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
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// Constant positive word offset from frame index
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
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return true;
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}
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}
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return false;
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}
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bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) {
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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ConstantSDNode *CN = 0;
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if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
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&& (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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&& (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
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// Constant word offset from a object in the data region
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Base = Addr.getOperand(0).getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
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return true;
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}
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}
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return false;
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}
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bool XCoreDAGToDAGISel::SelectADDRcpii(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) {
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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ConstantSDNode *CN = 0;
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if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
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&& (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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&& (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
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// Constant word offset from a object in the data region
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Base = Addr.getOperand(0).getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
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return true;
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}
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}
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return false;
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}
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SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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switch (N->getOpcode()) {
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default: break;
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case ISD::Constant: {
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uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
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if (immMskBitp(N)) {
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// Transformation function: get the size of a mask
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// Look for the first non-zero bit
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SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val));
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return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
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MVT::i32, MskSize);
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}
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else if (!isUInt<16>(Val)) {
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SDValue CPIdx =
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CurDAG->getTargetConstantPool(ConstantInt::get(
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Type::getInt32Ty(*CurDAG->getContext()), Val),
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TLI.getPointerTy());
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SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
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MVT::Other, CPIdx,
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CurDAG->getEntryNode());
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = MF->getMachineMemOperand(
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MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad, 4, 4);
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cast<MachineSDNode>(node)->setMemRefs(MemOp, MemOp + 1);
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return node;
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}
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break;
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}
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case XCoreISD::LADD: {
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SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
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N->getOperand(2) };
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return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
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Ops, 3);
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}
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case XCoreISD::LSUB: {
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SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
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N->getOperand(2) };
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return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
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Ops, 3);
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}
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case XCoreISD::MACCU: {
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SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
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N->getOperand(2), N->getOperand(3) };
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return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,
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Ops, 4);
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}
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case XCoreISD::MACCS: {
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SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
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N->getOperand(2), N->getOperand(3) };
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return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
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Ops, 4);
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}
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case XCoreISD::LMUL: {
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SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
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N->getOperand(2), N->getOperand(3) };
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return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
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Ops, 4);
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}
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case XCoreISD::CRC8: {
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SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
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return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32,
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Ops, 3);
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}
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case ISD::BRIND:
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if (SDNode *ResNode = SelectBRIND(N))
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return ResNode;
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break;
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// Other cases are autogenerated.
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}
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return SelectCode(N);
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}
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/// Given a chain return a new chain where any appearance of Old is replaced
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/// by New. There must be at most one instruction between Old and Chain and
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/// this instruction must be a TokenFactor. Returns an empty SDValue if
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/// these conditions don't hold.
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static SDValue
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replaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New)
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{
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if (Chain == Old)
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return New;
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if (Chain->getOpcode() != ISD::TokenFactor)
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return SDValue();
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SmallVector<SDValue, 8> Ops;
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bool found = false;
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for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) {
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if (Chain->getOperand(i) == Old) {
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Ops.push_back(New);
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found = true;
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} else {
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Ops.push_back(Chain->getOperand(i));
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}
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}
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if (!found)
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return SDValue();
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return CurDAG->getNode(ISD::TokenFactor, Chain->getDebugLoc(), MVT::Other,
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&Ops[0], Ops.size());
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}
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SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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// (brind (int_xcore_checkevent (addr)))
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SDValue Chain = N->getOperand(0);
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SDValue Addr = N->getOperand(1);
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if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
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return 0;
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unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue();
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if (IntNo != Intrinsic::xcore_checkevent)
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return 0;
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SDValue nextAddr = Addr->getOperand(2);
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SDValue CheckEventChainOut(Addr.getNode(), 1);
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if (!CheckEventChainOut.use_empty()) {
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// If the chain out of the checkevent intrinsic is an operand of the
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// indirect branch or used in a TokenFactor which is the operand of the
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// indirect branch then build a new chain which uses the chain coming into
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// the checkevent intrinsic instead.
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SDValue CheckEventChainIn = Addr->getOperand(0);
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SDValue NewChain = replaceInChain(CurDAG, Chain, CheckEventChainOut,
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CheckEventChainIn);
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if (!NewChain.getNode())
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return 0;
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Chain = NewChain;
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}
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// Enable events on the thread using setsr 1 and then disable them immediately
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// after with clrsr 1. If any resources owned by the thread are ready an event
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// will be taken. If no resource is ready we branch to the address which was
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// the operand to the checkevent intrinsic.
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SDValue constOne = getI32Imm(1);
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SDValue Glue =
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SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue,
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constOne, Chain), 0);
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Glue =
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SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue,
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constOne, Glue), 0);
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if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper &&
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nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
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return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other,
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nextAddr->getOperand(0), Glue);
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}
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return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue);
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}
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