llvm-6502/lib/Target/Mips/MipsSERegisterInfo.h
Bill Wendling 41e632d9e1 Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 07:04:14 +00:00

42 lines
1.2 KiB
C++

//===-- MipsSERegisterInfo.h - Mips32/64 Register Information ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Mips32/64 implementation of the TargetRegisterInfo
// class.
//
//===----------------------------------------------------------------------===//
#ifndef MIPSSEREGISTERINFO_H
#define MIPSSEREGISTERINFO_H
#include "MipsRegisterInfo.h"
namespace llvm {
class MipsSEInstrInfo;
class MipsSERegisterInfo : public MipsRegisterInfo {
public:
MipsSERegisterInfo(const MipsSubtarget &Subtarget);
bool requiresRegisterScavenging(const MachineFunction &MF) const;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
virtual const TargetRegisterClass *intRegClass(unsigned Size) const;
private:
virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
int FrameIndex, uint64_t StackSize,
int64_t SPOffset) const;
};
} // end namespace llvm
#endif