mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
5ca53a7ad8
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77218 91177308-0d34-0410-b5e6-96231b3b80d8
807 lines
28 KiB
C++
807 lines
28 KiB
C++
//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Base ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMBaseInstrInfo.h"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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static cl::opt<bool>
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EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
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cl::desc("Enable ARM 2-addr to 3-addr conv"));
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ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &sti)
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: TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
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STI(sti) {
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}
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MachineInstr *
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ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const {
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if (!EnableARM3Addr)
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return NULL;
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MachineInstr *MI = MBBI;
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MachineFunction &MF = *MI->getParent()->getParent();
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unsigned TSFlags = MI->getDesc().TSFlags;
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bool isPre = false;
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switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
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default: return NULL;
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case ARMII::IndexModePre:
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isPre = true;
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break;
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case ARMII::IndexModePost:
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break;
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}
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// Try splitting an indexed load/store to an un-indexed one plus an add/sub
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// operation.
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unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
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if (MemOpc == 0)
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return NULL;
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MachineInstr *UpdateMI = NULL;
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MachineInstr *MemMI = NULL;
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unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
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const TargetInstrDesc &TID = MI->getDesc();
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unsigned NumOps = TID.getNumOperands();
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bool isLoad = !TID.mayStore();
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const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
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const MachineOperand &Base = MI->getOperand(2);
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const MachineOperand &Offset = MI->getOperand(NumOps-3);
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unsigned WBReg = WB.getReg();
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unsigned BaseReg = Base.getReg();
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unsigned OffReg = Offset.getReg();
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unsigned OffImm = MI->getOperand(NumOps-2).getImm();
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ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
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switch (AddrMode) {
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default:
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assert(false && "Unknown indexed op!");
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return NULL;
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case ARMII::AddrMode2: {
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bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
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unsigned Amt = ARM_AM::getAM2Offset(OffImm);
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if (OffReg == 0) {
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if (ARM_AM::getSOImmVal(Amt) == -1)
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// Can't encode it in a so_imm operand. This transformation will
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// add more than 1 instruction. Abandon!
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return NULL;
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UpdateMI = BuildMI(MF, MI->getDebugLoc(),
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get(isSub ? getOpcode(ARMII::SUBri) :
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getOpcode(ARMII::ADDri)), WBReg)
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.addReg(BaseReg).addImm(Amt)
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.addImm(Pred).addReg(0).addReg(0);
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} else if (Amt != 0) {
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ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
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unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
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UpdateMI = BuildMI(MF, MI->getDebugLoc(),
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get(isSub ? getOpcode(ARMII::SUBrs) :
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getOpcode(ARMII::ADDrs)), WBReg)
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.addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
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.addImm(Pred).addReg(0).addReg(0);
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} else
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UpdateMI = BuildMI(MF, MI->getDebugLoc(),
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get(isSub ? getOpcode(ARMII::SUBrr) :
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getOpcode(ARMII::ADDrr)), WBReg)
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.addReg(BaseReg).addReg(OffReg)
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.addImm(Pred).addReg(0).addReg(0);
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break;
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}
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case ARMII::AddrMode3 : {
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bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
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unsigned Amt = ARM_AM::getAM3Offset(OffImm);
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if (OffReg == 0)
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// Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
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UpdateMI = BuildMI(MF, MI->getDebugLoc(),
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get(isSub ? getOpcode(ARMII::SUBri) :
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getOpcode(ARMII::ADDri)), WBReg)
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.addReg(BaseReg).addImm(Amt)
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.addImm(Pred).addReg(0).addReg(0);
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else
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UpdateMI = BuildMI(MF, MI->getDebugLoc(),
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get(isSub ? getOpcode(ARMII::SUBrr) :
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getOpcode(ARMII::ADDrr)), WBReg)
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.addReg(BaseReg).addReg(OffReg)
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.addImm(Pred).addReg(0).addReg(0);
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break;
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}
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}
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std::vector<MachineInstr*> NewMIs;
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if (isPre) {
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if (isLoad)
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MemMI = BuildMI(MF, MI->getDebugLoc(),
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get(MemOpc), MI->getOperand(0).getReg())
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.addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
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else
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MemMI = BuildMI(MF, MI->getDebugLoc(),
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get(MemOpc)).addReg(MI->getOperand(1).getReg())
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.addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
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NewMIs.push_back(MemMI);
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NewMIs.push_back(UpdateMI);
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} else {
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if (isLoad)
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MemMI = BuildMI(MF, MI->getDebugLoc(),
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get(MemOpc), MI->getOperand(0).getReg())
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.addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
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else
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MemMI = BuildMI(MF, MI->getDebugLoc(),
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get(MemOpc)).addReg(MI->getOperand(1).getReg())
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.addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
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if (WB.isDead())
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UpdateMI->getOperand(0).setIsDead();
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NewMIs.push_back(UpdateMI);
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NewMIs.push_back(MemMI);
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}
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// Transfer LiveVariables states, kill / dead info.
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if (LV) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() &&
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TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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unsigned Reg = MO.getReg();
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LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
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if (MO.isDef()) {
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MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
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if (MO.isDead())
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LV->addVirtualRegisterDead(Reg, NewMI);
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}
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if (MO.isUse() && MO.isKill()) {
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for (unsigned j = 0; j < 2; ++j) {
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// Look at the two new MI's in reverse order.
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MachineInstr *NewMI = NewMIs[j];
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if (!NewMI->readsRegister(Reg))
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continue;
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LV->addVirtualRegisterKilled(Reg, NewMI);
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if (VI.removeKill(MI))
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VI.Kills.push_back(NewMI);
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break;
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}
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}
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}
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}
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}
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MFI->insert(MBBI, NewMIs[1]);
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MFI->insert(MBBI, NewMIs[0]);
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return NewMIs[0];
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}
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// Branch analysis.
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bool
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ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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unsigned LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (isUncondBranchOpcode(LastOpc)) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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if (isCondBranchOpcode(LastOpc)) {
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(0).getMBB();
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Cond.push_back(LastInst->getOperand(1));
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Cond.push_back(LastInst->getOperand(2));
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return false;
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}
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return true; // Can't handle indirect branch.
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with a B and a Bcc, handle it.
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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Cond.push_back(SecondLastInst->getOperand(1));
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Cond.push_back(SecondLastInst->getOperand(2));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it. The second
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// one is not executed, so remove it.
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if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return false;
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}
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// ...likewise if it ends with a branch table followed by an unconditional
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// branch. The branch folder can create these, and we must get rid of them for
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// correctness of Thumb constant islands.
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if ((SecondLastOpc == ARM::BR_JTr ||
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SecondLastOpc == ARM::BR_JTm ||
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SecondLastOpc == ARM::BR_JTadd ||
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SecondLastOpc == ARM::tBR_JTr ||
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SecondLastOpc == ARM::t2BR_JT) &&
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isUncondBranchOpcode(LastOpc)) {
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return true;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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if (!isUncondBranchOpcode(I->getOpcode()) &&
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!isCondBranchOpcode(I->getOpcode()))
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return 1;
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--I;
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if (!isCondBranchOpcode(I->getOpcode()))
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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unsigned
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ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// FIXME this should probably have a DebugLoc argument
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DebugLoc dl = DebugLoc::getUnknownLoc();
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int BOpc = !STI.isThumb()
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? ARM::B : (STI.isThumb2() ? ARM::t2B : ARM::tB);
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int BccOpc = !STI.isThumb()
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? ARM::Bcc : (STI.isThumb2() ? ARM::t2Bcc : ARM::tBcc);
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"ARM branch conditions have two components!");
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch?
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BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
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else
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BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
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return 1;
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}
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// Two-way conditional branch.
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BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
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BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
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return 2;
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}
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bool ARMBaseInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
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Cond[0].setImm(ARMCC::getOppositeCondition(CC));
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return false;
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}
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bool ARMBaseInstrInfo::
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PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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unsigned Opc = MI->getOpcode();
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if (isUncondBranchOpcode(Opc)) {
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MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
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MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
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MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
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return true;
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}
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int PIdx = MI->findFirstPredOperandIdx();
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if (PIdx != -1) {
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MachineOperand &PMO = MI->getOperand(PIdx);
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PMO.setImm(Pred[0].getImm());
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MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
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return true;
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}
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return false;
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}
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bool ARMBaseInstrInfo::
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SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const {
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if (Pred1.size() > 2 || Pred2.size() > 2)
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return false;
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ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
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ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
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if (CC1 == CC2)
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return true;
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switch (CC1) {
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default:
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return false;
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case ARMCC::AL:
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return true;
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case ARMCC::HS:
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return CC2 == ARMCC::HI;
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case ARMCC::LS:
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return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
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case ARMCC::GE:
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return CC2 == ARMCC::GT;
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case ARMCC::LE:
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return CC2 == ARMCC::LT;
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}
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}
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bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const {
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
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return false;
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bool Found = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() == ARM::CPSR) {
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Pred.push_back(MO);
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Found = true;
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}
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}
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return Found;
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}
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/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
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static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
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unsigned JTI) DISABLE_INLINE;
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static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
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unsigned JTI) {
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return JT[JTI].MBBs.size();
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}
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/// GetInstSize - Return the size of the specified MachineInstr.
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///
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unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
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const MachineBasicBlock &MBB = *MI->getParent();
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const MachineFunction *MF = MBB.getParent();
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const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
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// Basic size info comes from the TSFlags field.
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const TargetInstrDesc &TID = MI->getDesc();
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unsigned TSFlags = TID.TSFlags;
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switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
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default: {
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// If this machine instr is an inline asm, measure it.
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if (MI->getOpcode() == ARM::INLINEASM)
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return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
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if (MI->isLabel())
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return 0;
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switch (MI->getOpcode()) {
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default:
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llvm_unreachable("Unknown or unset size field for instr!");
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case TargetInstrInfo::IMPLICIT_DEF:
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case TargetInstrInfo::DECLARE:
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case TargetInstrInfo::DBG_LABEL:
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case TargetInstrInfo::EH_LABEL:
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return 0;
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}
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break;
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}
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case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
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case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
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case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
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case ARMII::SizeSpecial: {
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bool IsThumb1JT = false;
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switch (MI->getOpcode()) {
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case ARM::CONSTPOOL_ENTRY:
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// If this machine instr is a constant pool entry, its size is recorded as
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// operand #2.
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return MI->getOperand(2).getImm();
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case ARM::Int_eh_sjlj_setjmp:
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return 12;
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case ARM::tBR_JTr:
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IsThumb1JT = true;
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// Fallthrough
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case ARM::BR_JTr:
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case ARM::BR_JTm:
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case ARM::BR_JTadd:
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case ARM::t2BR_JT: {
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// These are jumptable branches, i.e. a branch followed by an inlined
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// jumptable. The size is 4 + 4 * number of entries.
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unsigned NumOps = TID.getNumOperands();
|
|
MachineOperand JTOP =
|
|
MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
|
|
unsigned JTI = JTOP.getIndex();
|
|
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
assert(JTI < JT.size());
|
|
// Thumb instructions are 2 byte aligned, but JT entries are 4 byte
|
|
// 4 aligned. The assembler / linker may add 2 byte padding just before
|
|
// the JT entries. The size does not include this padding; the
|
|
// constant islands pass does separate bookkeeping for it.
|
|
// FIXME: If we know the size of the function is less than (1 << 16) *2
|
|
// bytes, we can use 16-bit entries instead. Then there won't be an
|
|
// alignment issue.
|
|
return getNumJTEntries(JT, JTI) * 4 + (IsThumb1JT ? 2 : 4);
|
|
}
|
|
default:
|
|
// Otherwise, pseudo-instruction sizes are zero.
|
|
return 0;
|
|
}
|
|
}
|
|
}
|
|
return 0; // Not reached
|
|
}
|
|
|
|
/// Return true if the instruction is a register to register move and
|
|
/// leave the source and dest operands in the passed parameters.
|
|
///
|
|
bool
|
|
ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
|
|
unsigned &SrcReg, unsigned &DstReg,
|
|
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
|
|
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
|
|
|
|
switch (MI.getOpcode()) {
|
|
default: break;
|
|
case ARM::FCPYS:
|
|
case ARM::FCPYD:
|
|
case ARM::VMOVD:
|
|
case ARM::VMOVQ: {
|
|
SrcReg = MI.getOperand(1).getReg();
|
|
DstReg = MI.getOperand(0).getReg();
|
|
return true;
|
|
}
|
|
case ARM::MOVr:
|
|
case ARM::tMOVr:
|
|
case ARM::tMOVgpr2tgpr:
|
|
case ARM::tMOVtgpr2gpr:
|
|
case ARM::tMOVgpr2gpr:
|
|
case ARM::t2MOVr: {
|
|
assert(MI.getDesc().getNumOperands() >= 2 &&
|
|
MI.getOperand(0).isReg() &&
|
|
MI.getOperand(1).isReg() &&
|
|
"Invalid ARM MOV instruction");
|
|
SrcReg = MI.getOperand(1).getReg();
|
|
DstReg = MI.getOperand(0).getReg();
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
unsigned
|
|
ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
|
|
int &FrameIndex) const {
|
|
switch (MI->getOpcode()) {
|
|
default: break;
|
|
case ARM::LDR:
|
|
case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
|
|
if (MI->getOperand(1).isFI() &&
|
|
MI->getOperand(2).isReg() &&
|
|
MI->getOperand(3).isImm() &&
|
|
MI->getOperand(2).getReg() == 0 &&
|
|
MI->getOperand(3).getImm() == 0) {
|
|
FrameIndex = MI->getOperand(1).getIndex();
|
|
return MI->getOperand(0).getReg();
|
|
}
|
|
break;
|
|
case ARM::t2LDRi12:
|
|
case ARM::tRestore:
|
|
if (MI->getOperand(1).isFI() &&
|
|
MI->getOperand(2).isImm() &&
|
|
MI->getOperand(2).getImm() == 0) {
|
|
FrameIndex = MI->getOperand(1).getIndex();
|
|
return MI->getOperand(0).getReg();
|
|
}
|
|
break;
|
|
case ARM::FLDD:
|
|
case ARM::FLDS:
|
|
if (MI->getOperand(1).isFI() &&
|
|
MI->getOperand(2).isImm() &&
|
|
MI->getOperand(2).getImm() == 0) {
|
|
FrameIndex = MI->getOperand(1).getIndex();
|
|
return MI->getOperand(0).getReg();
|
|
}
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
unsigned
|
|
ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
|
|
int &FrameIndex) const {
|
|
switch (MI->getOpcode()) {
|
|
default: break;
|
|
case ARM::STR:
|
|
case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
|
|
if (MI->getOperand(1).isFI() &&
|
|
MI->getOperand(2).isReg() &&
|
|
MI->getOperand(3).isImm() &&
|
|
MI->getOperand(2).getReg() == 0 &&
|
|
MI->getOperand(3).getImm() == 0) {
|
|
FrameIndex = MI->getOperand(1).getIndex();
|
|
return MI->getOperand(0).getReg();
|
|
}
|
|
break;
|
|
case ARM::t2STRi12:
|
|
case ARM::tSpill:
|
|
if (MI->getOperand(1).isFI() &&
|
|
MI->getOperand(2).isImm() &&
|
|
MI->getOperand(2).getImm() == 0) {
|
|
FrameIndex = MI->getOperand(1).getIndex();
|
|
return MI->getOperand(0).getReg();
|
|
}
|
|
break;
|
|
case ARM::FSTD:
|
|
case ARM::FSTS:
|
|
if (MI->getOperand(1).isFI() &&
|
|
MI->getOperand(2).isImm() &&
|
|
MI->getOperand(2).getImm() == 0) {
|
|
FrameIndex = MI->getOperand(1).getIndex();
|
|
return MI->getOperand(0).getReg();
|
|
}
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
bool
|
|
ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned DestReg, unsigned SrcReg,
|
|
const TargetRegisterClass *DestRC,
|
|
const TargetRegisterClass *SrcRC) const {
|
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
|
|
|
if (DestRC != SrcRC) {
|
|
// Not yet supported!
|
|
return false;
|
|
}
|
|
|
|
if (DestRC == ARM::GPRRegisterClass)
|
|
AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
|
|
DestReg).addReg(SrcReg)));
|
|
else if (DestRC == ARM::SPRRegisterClass)
|
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
|
|
.addReg(SrcReg));
|
|
else if (DestRC == ARM::DPRRegisterClass)
|
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
|
|
.addReg(SrcReg));
|
|
else if (DestRC == ARM::QPRRegisterClass)
|
|
BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
|
|
else
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
void ARMBaseInstrInfo::
|
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned SrcReg, bool isKill, int FI,
|
|
const TargetRegisterClass *RC) const {
|
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
|
|
|
if (RC == ARM::GPRRegisterClass) {
|
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
|
|
.addReg(SrcReg, getKillRegState(isKill))
|
|
.addFrameIndex(FI).addReg(0).addImm(0));
|
|
} else if (RC == ARM::DPRRegisterClass) {
|
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
|
|
.addReg(SrcReg, getKillRegState(isKill))
|
|
.addFrameIndex(FI).addImm(0));
|
|
} else {
|
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
|
|
.addReg(SrcReg, getKillRegState(isKill))
|
|
.addFrameIndex(FI).addImm(0));
|
|
}
|
|
}
|
|
|
|
void ARMBaseInstrInfo::
|
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned DestReg, int FI,
|
|
const TargetRegisterClass *RC) const {
|
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
|
|
|
if (RC == ARM::GPRRegisterClass) {
|
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
|
|
.addFrameIndex(FI).addReg(0).addImm(0));
|
|
} else if (RC == ARM::DPRRegisterClass) {
|
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
|
|
.addFrameIndex(FI).addImm(0));
|
|
} else {
|
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
|
|
.addFrameIndex(FI).addImm(0));
|
|
}
|
|
}
|
|
|
|
MachineInstr *ARMBaseInstrInfo::
|
|
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
|
|
const SmallVectorImpl<unsigned> &Ops, int FI) const {
|
|
if (Ops.size() != 1) return NULL;
|
|
|
|
unsigned OpNum = Ops[0];
|
|
unsigned Opc = MI->getOpcode();
|
|
MachineInstr *NewMI = NULL;
|
|
if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
|
|
// If it is updating CPSR, then it cannot be folded.
|
|
if (MI->getOperand(4).getReg() != ARM::CPSR || MI->getOperand(4).isDead()) {
|
|
unsigned Pred = MI->getOperand(2).getImm();
|
|
unsigned PredReg = MI->getOperand(3).getReg();
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
bool isKill = MI->getOperand(1).isKill();
|
|
bool isUndef = MI->getOperand(1).isUndef();
|
|
if (Opc == ARM::MOVr)
|
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
|
|
.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
|
|
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
|
|
else // ARM::t2MOVr
|
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
|
|
.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
|
|
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
|
|
} else { // move -> load
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
bool isDead = MI->getOperand(0).isDead();
|
|
bool isUndef = MI->getOperand(0).isUndef();
|
|
if (Opc == ARM::MOVr)
|
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
|
|
.addReg(DstReg,
|
|
RegState::Define |
|
|
getDeadRegState(isDead) |
|
|
getUndefRegState(isUndef))
|
|
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
|
|
else // ARM::t2MOVr
|
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
|
|
.addReg(DstReg,
|
|
RegState::Define |
|
|
getDeadRegState(isDead) |
|
|
getUndefRegState(isUndef))
|
|
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
|
|
}
|
|
}
|
|
}
|
|
else if (Opc == ARM::FCPYS) {
|
|
unsigned Pred = MI->getOperand(2).getImm();
|
|
unsigned PredReg = MI->getOperand(3).getReg();
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
bool isKill = MI->getOperand(1).isKill();
|
|
bool isUndef = MI->getOperand(1).isUndef();
|
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
|
|
.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
|
|
.addFrameIndex(FI)
|
|
.addImm(0).addImm(Pred).addReg(PredReg);
|
|
} else { // move -> load
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
bool isDead = MI->getOperand(0).isDead();
|
|
bool isUndef = MI->getOperand(0).isUndef();
|
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
|
|
.addReg(DstReg,
|
|
RegState::Define |
|
|
getDeadRegState(isDead) |
|
|
getUndefRegState(isUndef))
|
|
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
|
|
}
|
|
}
|
|
else if (Opc == ARM::FCPYD) {
|
|
unsigned Pred = MI->getOperand(2).getImm();
|
|
unsigned PredReg = MI->getOperand(3).getReg();
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
bool isKill = MI->getOperand(1).isKill();
|
|
bool isUndef = MI->getOperand(1).isUndef();
|
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
|
|
.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
|
|
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
|
|
} else { // move -> load
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
bool isDead = MI->getOperand(0).isDead();
|
|
bool isUndef = MI->getOperand(0).isUndef();
|
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
|
|
.addReg(DstReg,
|
|
RegState::Define |
|
|
getDeadRegState(isDead) |
|
|
getUndefRegState(isUndef))
|
|
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
|
|
}
|
|
}
|
|
|
|
return NewMI;
|
|
}
|
|
|
|
MachineInstr*
|
|
ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
|
|
MachineInstr* MI,
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
MachineInstr* LoadMI) const {
|
|
// FIXME
|
|
return 0;
|
|
}
|
|
|
|
bool
|
|
ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
|
|
const SmallVectorImpl<unsigned> &Ops) const {
|
|
if (Ops.size() != 1) return false;
|
|
|
|
unsigned Opc = MI->getOpcode();
|
|
if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
|
|
// If it is updating CPSR, then it cannot be folded.
|
|
return MI->getOperand(4).getReg() != ARM::CPSR ||MI->getOperand(4).isDead();
|
|
} else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) {
|
|
return true;
|
|
} else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) {
|
|
return false; // FIXME
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
int ARMBaseInstrInfo::getMatchingCondBranchOpcode(int Opc) const {
|
|
if (Opc == ARM::B)
|
|
return ARM::Bcc;
|
|
else if (Opc == ARM::tB)
|
|
return ARM::tBcc;
|
|
else if (Opc == ARM::t2B)
|
|
return ARM::t2Bcc;
|
|
|
|
llvm_unreachable("Unknown unconditional branch opcode!");
|
|
return 0;
|
|
}
|
|
|