mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1fac6b50ea
instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
248 lines
12 KiB
TableGen
248 lines
12 KiB
TableGen
//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the Intel i386 architecture, referred to
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// here as the "X86" architecture.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget state.
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//
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def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
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"64-bit mode (x86_64)">;
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def ModeNaCl : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
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"Native Client mode">;
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//===----------------------------------------------------------------------===//
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// X86 Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
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"Enable conditional move instructions">;
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def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
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"Support POPCNT instruction">;
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def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
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"Enable MMX instructions">;
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def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
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"Enable SSE instructions",
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// SSE codegen depends on cmovs, and all
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// SSE1+ processors support them.
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[FeatureMMX, FeatureCMOV]>;
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def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
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"Enable SSE2 instructions",
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[FeatureSSE1]>;
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def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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"Enable SSE3 instructions",
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[FeatureSSE2]>;
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def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
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"Enable SSSE3 instructions",
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[FeatureSSE3]>;
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def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
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"Enable SSE 4.1 instructions",
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[FeatureSSSE3]>;
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def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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[FeatureSSE41, FeaturePOPCNT]>;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions",
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[FeatureMMX]>;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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"Enable 3DNow! Athlon instructions",
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[Feature3DNow]>;
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// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
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// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
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// without disabling 64-bit mode.
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def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
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"Support 64-bit instructions",
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[FeatureCMOV]>;
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def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
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"64-bit with cmpxchg16b",
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[Feature64Bit]>;
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def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
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"Bit testing of memory is slow">;
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def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
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"IsUAMemFast", "true",
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"Fast unaligned memory access">;
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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"Support SSE 4a instructions",
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[FeaturePOPCNT]>;
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def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
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"Enable AVX instructions">;
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def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true",
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"Enable carry-less multiplication instructions">;
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def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
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"Enable three-operand fused multiple-add">;
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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"Enable four-operand fused multiple-add">;
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def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
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"HasVectorUAMem", "true",
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"Allow unaligned memory operands on vector/SIMD instructions">;
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def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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"Enable AES instructions">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"i386", []>;
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def : Proc<"i486", []>;
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def : Proc<"i586", []>;
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def : Proc<"pentium", []>;
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def : Proc<"pentium-mmx", [FeatureMMX]>;
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def : Proc<"i686", []>;
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def : Proc<"pentiumpro", [FeatureCMOV]>;
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def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
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def : Proc<"pentium3", [FeatureSSE1]>;
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def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
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def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
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def : Proc<"pentium4", [FeatureSSE2]>;
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def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
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def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
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def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
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def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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def : Proc<"core2", [FeatureSSSE3, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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def : Proc<"penryn", [FeatureSSE41, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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def : Proc<"atom", [FeatureSSE3, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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// "Arrandale" along with corei3 and corei5
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def : Proc<"corei7", [FeatureSSE42, FeatureCMPXCHG16B,
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FeatureSlowBTMem, FeatureFastUAMem, FeatureAES]>;
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def : Proc<"nehalem", [FeatureSSE42, FeatureCMPXCHG16B,
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FeatureSlowBTMem, FeatureFastUAMem]>;
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// Westmere is a similar machine to nehalem with some additional features.
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// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
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def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B,
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FeatureSlowBTMem, FeatureFastUAMem, FeatureAES,
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FeatureCLMUL]>;
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// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
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// rather than a superset.
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// FIXME: Disabling AVX for now since it's not ready.
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def : Proc<"corei7-avx", [FeatureSSE42, FeatureCMPXCHG16B,
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FeatureAES, FeatureCLMUL]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [Feature3DNow]>;
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def : Proc<"k6-3", [Feature3DNow]>;
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def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
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Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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def : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A,
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Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSlowBTMem]>;
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def : Proc<"istanbul", [Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSSE4A, Feature3DNowA]>;
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def : Proc<"shanghai", [Feature3DNowA, FeatureCMPXCHG16B, FeatureSSE4A,
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Feature3DNowA]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip2", [Feature3DNow]>;
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def : Proc<"c3", [Feature3DNow]>;
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def : Proc<"c3-2", [FeatureSSE1]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "X86RegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "X86InstrInfo.td"
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def X86InstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Calling Conventions
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//===----------------------------------------------------------------------===//
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include "X86CallingConv.td"
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//===----------------------------------------------------------------------===//
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// Assembly Parser
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//===----------------------------------------------------------------------===//
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// Currently the X86 assembly parser only supports ATT syntax.
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def ATTAsmParser : AsmParser {
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string AsmParserClassName = "ATTAsmParser";
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int Variant = 0;
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// Discard comments in assembly strings.
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string CommentDelimiter = "#";
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// Recognize hard coded registers.
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string RegisterPrefix = "%";
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}
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//===----------------------------------------------------------------------===//
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// Assembly Printers
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//===----------------------------------------------------------------------===//
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// The X86 target supports two different syntaxes for emitting machine code.
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// This is controlled by the -x86-asm-syntax={att|intel}
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def ATTAsmWriter : AsmWriter {
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string AsmWriterClassName = "ATTInstPrinter";
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int Variant = 0;
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bit isMCAsmWriter = 1;
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}
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def IntelAsmWriter : AsmWriter {
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string AsmWriterClassName = "IntelInstPrinter";
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int Variant = 1;
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bit isMCAsmWriter = 1;
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}
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def X86 : Target {
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// Information about the instructions...
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let InstructionSet = X86InstrInfo;
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let AssemblyParsers = [ATTAsmParser];
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let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
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}
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