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4c3d3ecdf8
subreg_hireg of register pair Rp.
* lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New
DenseMap similar to PeepholeMap that additionally records subreg info
too.
(runOnMachineFunction): Record information in PeepholeDoubleRegsMap
and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to
the instruction Rx = COPY Rp1:logreg_subreg.
* test/CodeGen/Hexagon/remove_lsr.ll: New test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163214 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
3.4 KiB
LLVM
81 lines
3.4 KiB
LLVM
; Test fix for PR-13709.
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; CHECK: foo
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; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
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; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
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; Convert the sequence
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; r17:16 = lsr(r11:10, #32)
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; .. = r16
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; into
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; r17:16 = lsr(r11:10, #32)
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; .. = r11
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; This makes the lsr instruction dead and it gets removed subsequently
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; by a dead code removal pass.
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%union.vect64 = type { i64 }
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%union.vect32 = type { i32 }
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define void @foo(%union.vect64* nocapture %sss_extracted_bit_rx_data_ptr,
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%union.vect32* nocapture %s_even, %union.vect32* nocapture %s_odd,
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i8* nocapture %scr_s_even_code_ptr, i8* nocapture %scr_s_odd_code_ptr)
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nounwind {
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entry:
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%scevgep = getelementptr %union.vect64* %sss_extracted_bit_rx_data_ptr, i32 1
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%scevgep28 = getelementptr %union.vect32* %s_odd, i32 1
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%scevgep32 = getelementptr %union.vect32* %s_even, i32 1
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%scevgep36 = getelementptr i8* %scr_s_odd_code_ptr, i32 1
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%scevgep39 = getelementptr i8* %scr_s_even_code_ptr, i32 1
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%lsr.iv42 = phi i32 [ %lsr.iv.next, %for.body ], [ 2, %entry ]
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%lsr.iv40 = phi i8* [ %scevgep41, %for.body ], [ %scevgep39, %entry ]
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%lsr.iv37 = phi i8* [ %scevgep38, %for.body ], [ %scevgep36, %entry ]
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%lsr.iv33 = phi %union.vect32* [ %scevgep34, %for.body ], [ %scevgep32, %entry ]
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%lsr.iv29 = phi %union.vect32* [ %scevgep30, %for.body ], [ %scevgep28, %entry ]
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%lsr.iv = phi %union.vect64* [ %scevgep26, %for.body ], [ %scevgep, %entry ]
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%predicate_1.023 = phi i8 [ undef, %entry ], [ %10, %for.body ]
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%predicate.022 = phi i8 [ undef, %entry ], [ %9, %for.body ]
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%val.021 = phi i64 [ undef, %entry ], [ %srcval, %for.body ]
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%lsr.iv3335 = bitcast %union.vect32* %lsr.iv33 to i32*
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%lsr.iv2931 = bitcast %union.vect32* %lsr.iv29 to i32*
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%lsr.iv27 = bitcast %union.vect64* %lsr.iv to i64*
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%0 = tail call i64 @llvm.hexagon.A2.vsubhs(i64 0, i64 %val.021)
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%conv3 = sext i8 %predicate.022 to i32
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%1 = trunc i64 %val.021 to i32
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%2 = trunc i64 %0 to i32
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%3 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv3, i32 %1, i32 %2)
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store i32 %3, i32* %lsr.iv3335, align 4, !tbaa !0
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%conv8 = sext i8 %predicate_1.023 to i32
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%4 = lshr i64 %val.021, 32
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%5 = trunc i64 %4 to i32
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%6 = lshr i64 %0, 32
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%7 = trunc i64 %6 to i32
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%8 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv8, i32 %5, i32 %7)
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store i32 %8, i32* %lsr.iv2931, align 4, !tbaa !0
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%srcval = load i64* %lsr.iv27, align 8
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%9 = load i8* %lsr.iv40, align 1, !tbaa !1
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%10 = load i8* %lsr.iv37, align 1, !tbaa !1
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%lftr.wideiv = trunc i32 %lsr.iv42 to i8
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%exitcond = icmp eq i8 %lftr.wideiv, 32
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%scevgep26 = getelementptr %union.vect64* %lsr.iv, i32 1
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%scevgep30 = getelementptr %union.vect32* %lsr.iv29, i32 1
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%scevgep34 = getelementptr %union.vect32* %lsr.iv33, i32 1
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%scevgep38 = getelementptr i8* %lsr.iv37, i32 1
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%scevgep41 = getelementptr i8* %lsr.iv40, i32 1
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%lsr.iv.next = add i32 %lsr.iv42, 1
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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declare i64 @llvm.hexagon.A2.vsubhs(i64, i64) nounwind readnone
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declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) nounwind readnone
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!0 = metadata !{metadata !"long", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
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