llvm-6502/test/CodeGen
Dale Johannesen 5cfd4ddece PowerPC inline asm was emitting two output operands
for a single "m" constraint; this is wrong because the
opcode of a load or store would have to change in parallel.
This patch makes it always compute addresses into a register,
which is correct but not as efficient as possible.  7144566.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79292 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18 00:18:39 +00:00
..
Alpha
ARM Reapply r79127. It was fixed by d0k. 2009-08-15 21:21:19 +00:00
Blackfin Add XFAIL testcase for setcc undef. 2009-08-15 12:10:22 +00:00
CBackend
CellSPU
CPP
Generic
Mips reintroduce support for Mips "small" section handling. This is 2009-08-13 06:28:06 +00:00
MSP430
PIC16 this passes. 2009-08-06 03:55:49 +00:00
PowerPC PowerPC inline asm was emitting two output operands 2009-08-18 00:18:39 +00:00
SPARC
SystemZ Various AsmWriter output cleanups. Use WriteAsOperand instead of 2009-08-13 01:36:44 +00:00
Thumb tPOP_RET now has predicate operands. 2009-08-13 06:05:07 +00:00
Thumb2 Fix tests. 2009-08-15 08:23:11 +00:00
X86 Fix test on Linux. 2009-08-15 21:28:17 +00:00
XCore Update getSectionForConstant() to to allow mergable sections to be nulled out 2009-08-17 16:37:11 +00:00