llvm-6502/test/CodeGen/Thumb2/thumb2-cbnz.ll
Evan Cheng 86050dc8cc Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:09:54 +00:00

34 lines
969 B
LLVM

; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
; rdar://7354379
declare double @floor(double) nounwind readnone
define void @t(i1 %a, double %b) {
entry:
br i1 %a, label %bb3, label %bb1
bb1: ; preds = %entry
unreachable
bb3: ; preds = %entry
br i1 %a, label %bb7, label %bb5
bb5: ; preds = %bb3
unreachable
bb7: ; preds = %bb3
br i1 %a, label %bb11, label %bb9
bb9: ; preds = %bb7
; CHECK: cmp r0, #0
; CHECK: cmp r0, #0
; CHECK-NEXT: cbnz
%0 = tail call double @floor(double %b) nounwind readnone ; <double> [#uses=0]
br label %bb11
bb11: ; preds = %bb9, %bb7
%1 = getelementptr i32* undef, i32 0
store i32 0, i32* %1
ret void
}