mirror of
https://github.com/c64scene-ar/llvm-6502.git
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5d1a38cbfa
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
244 lines
9.8 KiB
TableGen
244 lines
9.8 KiB
TableGen
//====- X86InstrXOP.td - Describe the X86 Instruction Set --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes XOP (eXtended OPerations)
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//
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//===----------------------------------------------------------------------===//
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multiclass xop2op<bits<8> opc, string OpcodeStr, X86MemOperand x86memop> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[]>, VEX;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[]>, VEX;
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}
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let isAsmParserOnly = 1 in {
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defm VPHSUBWD : xop2op<0xE2, "vphsubwd", f128mem>;
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defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", f128mem>;
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defm VPHSUBBW : xop2op<0xE1, "vphsubbw", f128mem>;
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defm VPHADDWQ : xop2op<0xC7, "vphaddwq", f128mem>;
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defm VPHADDWD : xop2op<0xC6, "vphaddwd", f128mem>;
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defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", f128mem>;
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defm VPHADDUWD : xop2op<0xD6, "vphadduwd", f128mem>;
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defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", f128mem>;
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defm VPHADDUBW : xop2op<0xD1, "vphaddubw", f128mem>;
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defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", f128mem>;
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defm VPHADDUBD : xop2op<0xD2, "vphaddubd", f128mem>;
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defm VPHADDDQ : xop2op<0xCB, "vphadddq", f128mem>;
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defm VPHADDBW : xop2op<0xC1, "vphaddbw", f128mem>;
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defm VPHADDBQ : xop2op<0xC3, "vphaddbq", f128mem>;
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defm VPHADDBD : xop2op<0xC2, "vphaddbd", f128mem>;
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defm VFRCZSS : xop2op<0x82, "vfrczss", f32mem>;
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defm VFRCZSD : xop2op<0x83, "vfrczsd", f64mem>;
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defm VFRCZPS : xop2op<0x80, "vfrczps", f128mem>;
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defm VFRCZPD : xop2op<0x81, "vfrczpd", f128mem>;
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}
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multiclass xop2op256<bits<8> opc, string OpcodeStr> {
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def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[]>, VEX, VEX_L;
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def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[]>, VEX;
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}
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let isAsmParserOnly = 1 in {
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defm VFRCZPS : xop2op256<0x80, "vfrczps">;
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defm VFRCZPD : xop2op256<0x81, "vfrczpd">;
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}
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multiclass xop3op<bits<8> opc, string OpcodeStr> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4VOp3;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V, VEX_W;
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def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
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(ins f128mem:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4VOp3;
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}
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let isAsmParserOnly = 1 in {
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defm VPSHLW : xop3op<0x95, "vpshlw">;
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defm VPSHLQ : xop3op<0x97, "vpshlq">;
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defm VPSHLD : xop3op<0x96, "vpshld">;
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defm VPSHLB : xop3op<0x94, "vpshlb">;
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defm VPSHAW : xop3op<0x99, "vpshaw">;
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defm VPSHAQ : xop3op<0x9B, "vpshaq">;
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defm VPSHAD : xop3op<0x9A, "vpshad">;
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defm VPSHAB : xop3op<0x98, "vpshab">;
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defm VPROTW : xop3op<0x91, "vprotw">;
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defm VPROTQ : xop3op<0x93, "vprotq">;
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defm VPROTD : xop3op<0x92, "vprotd">;
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defm VPROTB : xop3op<0x90, "vprotb">;
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}
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multiclass xop3opimm<bits<8> opc, string OpcodeStr> {
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins f128mem:$src1, i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX;
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}
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let isAsmParserOnly = 1 in {
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defm VPROTW : xop3opimm<0xC1, "vprotw">;
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defm VPROTQ : xop3opimm<0xC3, "vprotq">;
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defm VPROTD : xop3opimm<0xC2, "vprotd">;
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defm VPROTB : xop3opimm<0xC0, "vprotb">;
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}
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// Instruction where second source can be memory, but third must be register
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multiclass xop4opm2<bits<8> opc, string OpcodeStr> {
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def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM;
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def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM;
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}
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let isAsmParserOnly = 1 in {
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defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd">;
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defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd">;
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defm VPMACSWW : xop4opm2<0x95, "vpmacsww">;
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defm VPMACSWD : xop4opm2<0x96, "vpmacswd">;
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defm VPMACSSWW : xop4opm2<0x85, "vpmacssww">;
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defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd">;
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defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql">;
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defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh">;
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defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd">;
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defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql">;
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defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh">;
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defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd">;
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}
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// Instruction where second source can be memory, third must be imm8
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multiclass xop4opimm<bits<8> opc, string OpcodeStr> {
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V;
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}
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let isAsmParserOnly = 1 in {
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defm VPCOMW : xop4opimm<0xCD, "vpcomw">;
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defm VPCOMUW : xop4opimm<0xED, "vpcomuw">;
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defm VPCOMUQ : xop4opimm<0xEF, "vpcomuq">;
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defm VPCOMUD : xop4opimm<0xEE, "vpcomud">;
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defm VPCOMUB : xop4opimm<0xEC, "vpcomub">;
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defm VPCOMQ : xop4opimm<0xCF, "vpcomq">;
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defm VPCOMD : xop4opimm<0xCE, "vpcomd">;
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defm VPCOMB : xop4opimm<0xCC, "vpcomb">;
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}
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// Instruction where either second or third source can be memory
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multiclass xop4op<bits<8> opc, string OpcodeStr> {
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def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM;
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def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
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def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM;
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}
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let isAsmParserOnly = 1 in {
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defm VPPERM : xop4op<0xA3, "vpperm">;
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defm VPCMOV : xop4op<0xA2, "vpcmov">;
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}
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multiclass xop4op256<bits<8> opc, string OpcodeStr> {
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def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM;
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def rmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
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def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM;
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}
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let isAsmParserOnly = 1 in {
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defm VPCMOV : xop4op256<0xA2, "vpcmov">;
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}
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multiclass xop5op<bits<8> opc, string OpcodeStr> {
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def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[]>;
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def rm : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[]>, VEX_W, MemOp4;
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def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[]>;
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def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[]>;
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def rmY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[]>, VEX_W, MemOp4;
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def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[]>;
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}
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let isAsmParserOnly = 1 in {
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defm VPERMIL2PD : xop5op<0x49, "vpermil2pd">;
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defm VPERMIL2PS : xop5op<0x48, "vpermil2ps">;
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}
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