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905e33545c
default architecture for reasonable modern x86 processors, actually be modern. This processor model should essentially be "tuned" for modern x86 chips as much as possible without undue penalties on any specific architecture. Previously we weren't even using the nice scheduling models. There are a few other tweaks needed here, but this change at least I have benchmarked across a decent swatch of chips (intel's clovertown, westmere, and sandybridge; amd's istanbul) and seen no significant regressions. If anyone has suggested ways to test this, just let me know. Somewhat alarmingly, no existing tests failed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208230 91177308-0d34-0410-b5e6-96231b3b80d8
436 lines
21 KiB
TableGen
436 lines
21 KiB
TableGen
//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the Intel i386 architecture, referred
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// to here as the "X86" architecture.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget state
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//
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def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
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"64-bit mode (x86_64)">;
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def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
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"32-bit mode (80386)">;
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def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
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"16-bit mode (i8086)">;
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//===----------------------------------------------------------------------===//
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// X86 Subtarget features
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//===----------------------------------------------------------------------===//
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
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"Enable conditional move instructions">;
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def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
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"Support POPCNT instruction">;
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def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
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"Enable MMX instructions">;
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def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
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"Enable SSE instructions",
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// SSE codegen depends on cmovs, and all
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// SSE1+ processors support them.
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[FeatureMMX, FeatureCMOV]>;
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def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
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"Enable SSE2 instructions",
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[FeatureSSE1]>;
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def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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"Enable SSE3 instructions",
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[FeatureSSE2]>;
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def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
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"Enable SSSE3 instructions",
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[FeatureSSE3]>;
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def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
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"Enable SSE 4.1 instructions",
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[FeatureSSSE3]>;
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def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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[FeatureSSE41]>;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions",
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[FeatureMMX]>;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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"Enable 3DNow! Athlon instructions",
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[Feature3DNow]>;
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// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
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// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
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// without disabling 64-bit mode.
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def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
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"Support 64-bit instructions",
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[FeatureCMOV]>;
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def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
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"64-bit with cmpxchg16b",
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[Feature64Bit]>;
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def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
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"Bit testing of memory is slow">;
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def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
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"SHLD instruction is slow">;
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def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
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"IsUAMemFast", "true",
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"Fast unaligned memory access">;
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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"Support SSE 4a instructions",
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[FeatureSSE3]>;
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def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
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"Enable AVX instructions",
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[FeatureSSE42]>;
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def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
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"Enable AVX2 instructions",
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[FeatureAVX]>;
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def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
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"Enable AVX-512 instructions",
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[FeatureAVX2]>;
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def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
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"Enable AVX-512 Exponential and Reciprocal Instructions",
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[FeatureAVX512]>;
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def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
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"Enable AVX-512 Conflict Detection Instructions",
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[FeatureAVX512]>;
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def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
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"Enable AVX-512 PreFetch Instructions",
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[FeatureAVX512]>;
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def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
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"Enable packed carry-less multiplication instructions",
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[FeatureSSE2]>;
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def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
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"Enable three-operand fused multiple-add",
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[FeatureAVX]>;
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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"Enable four-operand fused multiple-add",
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[FeatureAVX, FeatureSSE4A]>;
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def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
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"Enable XOP instructions",
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[FeatureFMA4]>;
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def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
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"HasVectorUAMem", "true",
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"Allow unaligned memory operands on vector/SIMD instructions">;
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def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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"Enable AES instructions",
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[FeatureSSE2]>;
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def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
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"Enable TBM instructions">;
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def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
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"Support MOVBE instruction">;
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def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
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"Support RDRAND instruction">;
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def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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"Support 16-bit floating point conversion instructions",
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[FeatureAVX]>;
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def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
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"Support FS/GS Base instructions">;
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def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
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"Support LZCNT instruction">;
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def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
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"Support BMI instructions">;
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def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
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"Support BMI2 instructions">;
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def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
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"Support RTM instructions">;
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def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
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"Support HLE">;
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def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
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"Support ADX instructions">;
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def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
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"Enable SHA instructions",
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[FeatureSSE2]>;
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def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
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"Support PRFCHW instructions">;
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def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
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"Support RDSEED instruction">;
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def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
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"Use LEA for adjusting the stack pointer">;
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def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
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"HasSlowDivide", "true",
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"Use small divide for positive values less than 256">;
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def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
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"PadShortFunctions", "true",
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"Pad short functions">;
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def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
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"CallRegIndirect", "true",
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"Call register indirect">;
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def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
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"LEA instruction needs inputs at AG stage">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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include "X86Schedule.td"
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def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
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"Intel Atom processors">;
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def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
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"Intel Silvermont processors">;
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class Proc<string Name, list<SubtargetFeature> Features>
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: ProcessorModel<Name, GenericModel, Features>;
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def : Proc<"generic", []>;
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def : Proc<"i386", []>;
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def : Proc<"i486", []>;
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def : Proc<"i586", []>;
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def : Proc<"pentium", []>;
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def : Proc<"pentium-mmx", [FeatureMMX]>;
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def : Proc<"i686", []>;
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def : Proc<"pentiumpro", [FeatureCMOV]>;
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def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
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def : Proc<"pentium3", [FeatureSSE1]>;
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def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
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def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
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def : Proc<"pentium4", [FeatureSSE2]>;
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def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
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// Intel Core Duo.
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def : ProcessorModel<"yonah", SandyBridgeModel,
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[FeatureSSE3, FeatureSlowBTMem]>;
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// NetBurst.
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def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
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def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
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// Intel Core 2 Solo/Duo.
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def : ProcessorModel<"core2", SandyBridgeModel,
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[FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
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def : ProcessorModel<"penryn", SandyBridgeModel,
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[FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
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// Atom.
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def : ProcessorModel<"atom", AtomModel,
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[ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
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FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
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FeatureSlowDivide,
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FeatureCallRegIndirect,
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FeatureLEAUsesAG,
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FeaturePadShortFunctions]>;
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// Atom Silvermont.
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def : ProcessorModel<"slm", SLMModel, [ProcIntelSLM,
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FeatureSSE42, FeatureCMPXCHG16B,
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FeatureMOVBE, FeaturePOPCNT,
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FeaturePCLMUL, FeatureAES,
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FeatureCallRegIndirect,
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FeaturePRFCHW,
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FeatureSlowBTMem, FeatureFastUAMem]>;
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// "Arrandale" along with corei3 and corei5
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def : ProcessorModel<"corei7", SandyBridgeModel,
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[FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
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FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
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def : ProcessorModel<"nehalem", SandyBridgeModel,
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[FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
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FeatureFastUAMem, FeaturePOPCNT]>;
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// Westmere is a similar machine to nehalem with some additional features.
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// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
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def : ProcessorModel<"westmere", SandyBridgeModel,
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[FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
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FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
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FeaturePCLMUL]>;
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// Sandy Bridge
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// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
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// rather than a superset.
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def : ProcessorModel<"corei7-avx", SandyBridgeModel,
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[FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
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FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
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// Ivy Bridge
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def : ProcessorModel<"core-avx-i", SandyBridgeModel,
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[FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
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FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
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FeatureF16C, FeatureFSGSBase]>;
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// Haswell
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def : ProcessorModel<"core-avx2", HaswellModel,
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[FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
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FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
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FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
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FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
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FeatureHLE]>;
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// KNL
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// FIXME: define KNL model
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def : ProcessorModel<"knl", HaswellModel,
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[FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
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FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
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FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
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FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
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FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [Feature3DNow]>;
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def : Proc<"k6-3", [Feature3DNow]>;
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def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"amdfam10", [FeatureSSE4A,
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Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
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FeaturePOPCNT, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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// Bobcat
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def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
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FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
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FeatureSlowSHLD]>;
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// Jaguar
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def : Proc<"btver2", [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
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FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
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FeatureBMI, FeatureF16C, FeatureMOVBE,
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FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>;
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// Bulldozer
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def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
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FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
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FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>;
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// Piledriver
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def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
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FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
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FeatureF16C, FeatureLZCNT,
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FeaturePOPCNT, FeatureBMI, FeatureTBM,
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FeatureFMA, FeatureSlowSHLD]>;
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// Steamroller
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def : Proc<"bdver3", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
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FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
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FeatureF16C, FeatureLZCNT,
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FeaturePOPCNT, FeatureBMI, FeatureTBM,
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FeatureFMA, FeatureFSGSBase]>;
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// Excavator
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def : Proc<"bdver4", [FeatureAVX2, FeatureXOP, FeatureFMA4,
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FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
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FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
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FeaturePOPCNT, FeatureBMI, FeatureBMI2,
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FeatureTBM, FeatureFMA, FeatureFSGSBase]>;
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def : Proc<"geode", [Feature3DNowA]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip2", [Feature3DNow]>;
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def : Proc<"c3", [Feature3DNow]>;
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def : Proc<"c3-2", [FeatureSSE1]>;
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// We also provide a generic 64-bit specific x86 processor model which tries to
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// be good for modern chips without enabling instruction set encodings past the
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// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
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// modern 64-bit x86 chip, and enables features that are generally beneficial.
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//
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// We currently use the Sandy Bridge model as the default scheduling model as
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// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
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// covers a huge swath of x86 processors. If there are specific scheduling
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// knobs which need to be tuned differently for AMD chips, we might consider
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// forming a common base for them.
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def : ProcessorModel<"x86-64", SandyBridgeModel,
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[FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
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FeatureFastUAMem]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "X86RegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "X86InstrInfo.td"
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def X86InstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Calling Conventions
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//===----------------------------------------------------------------------===//
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include "X86CallingConv.td"
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//===----------------------------------------------------------------------===//
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// Assembly Parser
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//===----------------------------------------------------------------------===//
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def ATTAsmParser : AsmParser {
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string AsmParserClassName = "AsmParser";
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}
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def ATTAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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// Variant name.
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string Name = "att";
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// Discard comments in assembly strings.
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string CommentDelimiter = "#";
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// Recognize hard coded registers.
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string RegisterPrefix = "%";
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}
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def IntelAsmParserVariant : AsmParserVariant {
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int Variant = 1;
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// Variant name.
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string Name = "intel";
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// Discard comments in assembly strings.
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string CommentDelimiter = ";";
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|
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// Recognize hard coded registers.
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|
string RegisterPrefix = "";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly Printers
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// The X86 target supports two different syntaxes for emitting machine code.
|
|
// This is controlled by the -x86-asm-syntax={att|intel}
|
|
def ATTAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "ATTInstPrinter";
|
|
int Variant = 0;
|
|
}
|
|
def IntelAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "IntelInstPrinter";
|
|
int Variant = 1;
|
|
}
|
|
|
|
def X86 : Target {
|
|
// Information about the instructions...
|
|
let InstructionSet = X86InstrInfo;
|
|
let AssemblyParsers = [ATTAsmParser];
|
|
let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
|
|
let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
|
|
}
|