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15acadde5f
running tail duplication when doing branch folding for if-conversion, and we also want to be able to run tail duplication earlier to fix some reg alloc problems. Move the CanFallThrough function from BranchFolding to MachineBasicBlock so that it can be shared by TailDuplication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89904 91177308-0d34-0410-b5e6-96231b3b80d8
370 lines
13 KiB
C++
370 lines
13 KiB
C++
//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LLVMTargetMachine class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Pass.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/GCStrategy.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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namespace llvm {
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bool EnableFastISel;
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}
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static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
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cl::desc("Disable Post Regalloc"));
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static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
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cl::desc("Disable branch folding"));
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static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
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cl::desc("Disable tail duplication"));
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static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
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cl::desc("Disable code placement"));
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static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
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cl::desc("Disable Stack Slot Coloring"));
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static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
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cl::desc("Disable Machine Sinking"));
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static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
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cl::desc("Disable Loop Strength Reduction Pass"));
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static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
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cl::desc("Disable Codegen Prepare"));
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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cl::desc("Print LLVM IR input to isel pass"));
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static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
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cl::desc("Dump emitter generated instructions as assembly"));
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static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
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cl::desc("Dump garbage collector data"));
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static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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cl::desc("Verify generated machine code"),
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cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
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// Enable or disable FastISel. Both options are needed, because
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// FastISel is enabled by default with -fast, and we wish to be
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// able to enable or disable fast-isel independently from -O0.
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static cl::opt<cl::boolOrDefault>
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EnableFastISelOption("fast-isel", cl::Hidden,
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cl::desc("Enable the \"fast\" instruction selector"));
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// Enable or disable an experimental optimization to split GEPs
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// and run a special GVN pass which does not examine loads, in
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// an effort to factor out redundancy implicit in complex GEPs.
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static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
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cl::desc("Split GEPs and run no-load GVN"));
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LLVMTargetMachine::LLVMTargetMachine(const Target &T,
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const std::string &TargetTriple)
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: TargetMachine(T) {
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AsmInfo = T.createAsmInfo(TargetTriple);
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}
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FileModel::Model
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LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
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formatted_raw_ostream &Out,
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CodeGenFileType FileType,
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CodeGenOpt::Level OptLevel) {
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// Add common CodeGen passes.
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if (addCommonCodeGenPasses(PM, OptLevel))
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return FileModel::Error;
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switch (FileType) {
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default:
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break;
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case TargetMachine::AssemblyFile:
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if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
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return FileModel::Error;
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return FileModel::AsmFile;
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case TargetMachine::ObjectFile:
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if (getMachOWriterInfo())
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return FileModel::MachOFile;
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else if (getELFWriterInfo())
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return FileModel::ElfFile;
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}
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return FileModel::Error;
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}
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bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool Verbose,
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formatted_raw_ostream &Out) {
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FunctionPass *Printer =
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getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose);
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if (!Printer)
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return true;
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PM.add(Printer);
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return false;
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}
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/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
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/// be split up (e.g., to add an object writer pass), this method can be used to
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/// finish up adding passes to emit the file, if necessary.
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bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
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MachineCodeEmitter *MCE,
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CodeGenOpt::Level OptLevel) {
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if (MCE)
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addSimpleCodeEmitter(PM, OptLevel, *MCE);
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if (PrintEmittedAsm)
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addAssemblyEmitter(PM, OptLevel, true, ferrs());
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PM.add(createGCInfoDeleter());
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return false; // success!
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}
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/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
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/// be split up (e.g., to add an object writer pass), this method can be used to
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/// finish up adding passes to emit the file, if necessary.
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bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
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JITCodeEmitter *JCE,
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CodeGenOpt::Level OptLevel) {
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if (JCE)
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addSimpleCodeEmitter(PM, OptLevel, *JCE);
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if (PrintEmittedAsm)
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addAssemblyEmitter(PM, OptLevel, true, ferrs());
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PM.add(createGCInfoDeleter());
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return false; // success!
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}
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/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
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/// be split up (e.g., to add an object writer pass), this method can be used to
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/// finish up adding passes to emit the file, if necessary.
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bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
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ObjectCodeEmitter *OCE,
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CodeGenOpt::Level OptLevel) {
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if (OCE)
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addSimpleCodeEmitter(PM, OptLevel, *OCE);
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if (PrintEmittedAsm)
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addAssemblyEmitter(PM, OptLevel, true, ferrs());
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PM.add(createGCInfoDeleter());
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return false; // success!
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}
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
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/// get machine code emitted. This uses a MachineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
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MachineCodeEmitter &MCE,
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CodeGenOpt::Level OptLevel) {
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// Add common CodeGen passes.
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if (addCommonCodeGenPasses(PM, OptLevel))
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return true;
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addCodeEmitter(PM, OptLevel, MCE);
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if (PrintEmittedAsm)
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addAssemblyEmitter(PM, OptLevel, true, ferrs());
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PM.add(createGCInfoDeleter());
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return false; // success!
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}
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
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/// get machine code emitted. This uses a MachineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
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JITCodeEmitter &JCE,
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CodeGenOpt::Level OptLevel) {
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// Add common CodeGen passes.
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if (addCommonCodeGenPasses(PM, OptLevel))
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return true;
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addCodeEmitter(PM, OptLevel, JCE);
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if (PrintEmittedAsm)
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addAssemblyEmitter(PM, OptLevel, true, ferrs());
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PM.add(createGCInfoDeleter());
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return false; // success!
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}
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static void printAndVerify(PassManagerBase &PM,
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const char *Banner,
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bool allowDoubleDefs = false) {
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(errs(), Banner));
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if (VerifyMachineCode)
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PM.add(createMachineVerifierPass(allowDoubleDefs));
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}
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/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
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/// emitting to assembly files or machine code output.
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///
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bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Standard LLVM-Level Passes.
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// Optionally, tun split-GEPs and no-load GVN.
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if (EnableSplitGEPGVN) {
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PM.add(createGEPSplitterPass());
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PM.add(createGVNPass(/*NoPRE=*/false, /*NoLoads=*/true));
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}
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// Run loop strength reduction before anything else.
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if (OptLevel != CodeGenOpt::None && !DisableLSR) {
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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if (PrintLSR)
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PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
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}
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// Turn exception handling constructs into something the code generators can
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// handle.
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switch (getMCAsmInfo()->getExceptionHandlingType())
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{
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case ExceptionHandling::SjLj:
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// SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
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PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
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PM.add(createSjLjEHPass(getTargetLowering()));
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break;
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case ExceptionHandling::Dwarf:
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PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
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break;
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case ExceptionHandling::None:
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PM.add(createLowerInvokePass(getTargetLowering()));
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break;
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}
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PM.add(createGCLoweringPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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if (OptLevel != CodeGenOpt::None && !DisableCGP)
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PM.add(createCodeGenPreparePass(getTargetLowering()));
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PM.add(createStackProtectorPass(getTargetLowering()));
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if (PrintISelInput)
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PM.add(createPrintFunctionPass("\n\n"
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"*** Final LLVM Code input to ISel ***\n",
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&errs()));
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// Standard Lower-Level Passes.
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// Set up a MachineFunction for the rest of CodeGen to work on.
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PM.add(new MachineFunctionAnalysis(*this, OptLevel));
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// Enable FastISel with -fast, but allow that to be overridden.
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if (EnableFastISelOption == cl::BOU_TRUE ||
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(OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
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EnableFastISel = true;
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// Ask the target for an isel.
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if (addInstSelector(PM, OptLevel))
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return true;
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// Print the instruction selected machine code...
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printAndVerify(PM, "After Instruction Selection",
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/* allowDoubleDefs= */ true);
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if (OptLevel != CodeGenOpt::None) {
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if (!DisableMachineLICM)
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PM.add(createMachineLICMPass());
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if (!DisableMachineSink)
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PM.add(createMachineSinkingPass());
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printAndVerify(PM, "After MachineLICM and MachineSinking",
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/* allowDoubleDefs= */ true);
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}
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// Run pre-ra passes.
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if (addPreRegAlloc(PM, OptLevel))
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printAndVerify(PM, "After PreRegAlloc passes",
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/* allowDoubleDefs= */ true);
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// Perform register allocation.
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PM.add(createRegisterAllocator());
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printAndVerify(PM, "After Register Allocation");
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// Perform stack slot coloring.
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if (OptLevel != CodeGenOpt::None && !DisableSSC) {
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// FIXME: Re-enable coloring with register when it's capable of adding
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// kill markers.
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PM.add(createStackSlotColoringPass(false));
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printAndVerify(PM, "After StackSlotColoring");
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}
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// Run post-ra passes.
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if (addPostRegAlloc(PM, OptLevel))
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printAndVerify(PM, "After PostRegAlloc passes");
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PM.add(createLowerSubregsPass());
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printAndVerify(PM, "After LowerSubregs");
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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printAndVerify(PM, "After PrologEpilogCodeInserter");
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// Run pre-sched2 passes.
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if (addPreSched2(PM, OptLevel))
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printAndVerify(PM, "After PreSched2 passes");
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// Second pass scheduler.
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if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
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PM.add(createPostRAScheduler(OptLevel));
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printAndVerify(PM, "After PostRAScheduler");
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}
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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printAndVerify(PM, "After BranchFolding");
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}
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// Tail duplication.
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if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
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PM.add(createTailDuplicationPass());
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printAndVerify(PM, "After TailDuplication");
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}
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PM.add(createGCMachineCodeAnalysisPass());
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if (PrintGCInfo)
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PM.add(createGCInfoPrinter(errs()));
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if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
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PM.add(createCodePlacementOptPass());
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printAndVerify(PM, "After CodePlacementOpt");
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}
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if (addPreEmitPass(PM, OptLevel))
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printAndVerify(PM, "After PreEmit passes");
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return false;
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}
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