mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-21 06:30:16 +00:00
886f0101a7
target-specific shuffl DAG combines. We were recognizing the paired shuffles backwards. This code needs to be replaced anyways as we have the same functionality elsewhere, but I'll do the refactoring in a follow-up, this is the minimal fix to the behavior. In addition to fixing miscompiles with the new vector shuffle lowering, it also causes the canonicalization to kick in much better, selecting the smaller encoding variants in lots of places in the new AVX path. This still isn't quite ideal as we don't need both the shufpd and the punpck instructions, but that'll get fixed in a follow-up patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215690 91177308-0d34-0410-b5e6-96231b3b80d8
200 lines
4.1 KiB
LLVM
200 lines
4.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=pentium4 | FileCheck %s -check-prefix=SSE2
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define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
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; AVX: sext_8i16_to_8i32
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; AVX: vpmovsxwd
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%B = sext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
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; AVX: sext_4i32_to_4i64
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; AVX: vpmovsxdq
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%B = sext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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; AVX: load_sext_test1
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; AVX: vpmovsxwd (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test1
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; SSSE3: movq
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; SSSE3: punpcklwd %xmm{{.*}}, %xmm{{.*}}
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; SSSE3: psrad $16
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; SSSE3: ret
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; SSE2: load_sext_test1
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; SSE2: movq
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; SSE2: punpcklwd %xmm{{.*}}, %xmm{{.*}}
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; SSE2: psrad $16
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; SSE2: ret
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define <4 x i32> @load_sext_test1(<4 x i16> *%ptr) {
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%X = load <4 x i16>* %ptr
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%Y = sext <4 x i16> %X to <4 x i32>
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ret <4 x i32>%Y
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}
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; AVX: load_sext_test2
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; AVX: vpmovsxbd (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test2
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; SSSE3: movd
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; SSSE3: pshufb
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; SSSE3: psrad $24
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; SSSE3: ret
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; SSE2: load_sext_test2
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; SSE2: movl
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; SSE2: psrad $24
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; SSE2: ret
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define <4 x i32> @load_sext_test2(<4 x i8> *%ptr) {
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%X = load <4 x i8>* %ptr
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%Y = sext <4 x i8> %X to <4 x i32>
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ret <4 x i32>%Y
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}
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; AVX: load_sext_test3
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; AVX: vpmovsxbq (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test3
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; SSSE3: movsbq
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; SSSE3: movsbq
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; SSSE3: punpcklqdq
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; SSSE3: ret
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; SSE2: load_sext_test3
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; SSE2: movsbq
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; SSE2: movsbq
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; SSE2: punpcklqdq
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; SSE2: ret
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define <2 x i64> @load_sext_test3(<2 x i8> *%ptr) {
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%X = load <2 x i8>* %ptr
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%Y = sext <2 x i8> %X to <2 x i64>
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ret <2 x i64>%Y
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}
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; AVX: load_sext_test4
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; AVX: vpmovsxwq (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test4
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; SSSE3: movswq
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; SSSE3: movswq
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; SSSE3: punpcklqdq
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; SSSE3: ret
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; SSE2: load_sext_test4
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; SSE2: movswq
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; SSE2: movswq
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; SSE2: punpcklqdq
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; SSE2: ret
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define <2 x i64> @load_sext_test4(<2 x i16> *%ptr) {
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%X = load <2 x i16>* %ptr
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%Y = sext <2 x i16> %X to <2 x i64>
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ret <2 x i64>%Y
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}
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; AVX: load_sext_test5
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; AVX: vpmovsxdq (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test5
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; SSSE3: movslq
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; SSSE3: movslq
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; SSSE3: punpcklqdq
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; SSSE3: ret
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; SSE2: load_sext_test5
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; SSE2: movslq
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; SSE2: movslq
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; SSE2: punpcklqdq
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; SSE2: ret
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define <2 x i64> @load_sext_test5(<2 x i32> *%ptr) {
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%X = load <2 x i32>* %ptr
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%Y = sext <2 x i32> %X to <2 x i64>
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ret <2 x i64>%Y
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}
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; AVX: load_sext_test6
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; AVX: vpmovsxbw (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test6
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; SSSE3: movq
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; SSSE3: punpcklbw
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; SSSE3: psraw $8
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; SSSE3: ret
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; SSE2: load_sext_test6
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; SSE2: movq
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; SSE2: punpcklbw
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; SSE2: psraw $8
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; SSE2: ret
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define <8 x i16> @load_sext_test6(<8 x i8> *%ptr) {
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%X = load <8 x i8>* %ptr
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%Y = sext <8 x i8> %X to <8 x i16>
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ret <8 x i16>%Y
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}
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; AVX: sext_4i1_to_4i64
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; AVX: vpslld $31
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; AVX: vpsrad $31
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; AVX: vpmovsxdq
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; AVX: vpmovsxdq
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; AVX: ret
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define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) {
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%extmask = sext <4 x i1> %mask to <4 x i64>
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ret <4 x i64> %extmask
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}
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; AVX-LABEL: sext_16i8_to_16i16
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; AVX: vpmovsxbw
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; AVX: vpunpckhqdq
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; AVX: vpmovsxbw
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; AVX: ret
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define <16 x i16> @sext_16i8_to_16i16(<16 x i8> *%ptr) {
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%X = load <16 x i8>* %ptr
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%Y = sext <16 x i8> %X to <16 x i16>
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ret <16 x i16> %Y
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}
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; AVX: sext_4i8_to_4i64
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; AVX: vpslld $24
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; AVX: vpsrad $24
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; AVX: vpmovsxdq
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; AVX: vpmovsxdq
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; AVX: ret
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define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) {
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%extmask = sext <4 x i8> %mask to <4 x i64>
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ret <4 x i64> %extmask
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}
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; AVX: sext_4i8_to_4i64
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; AVX: vpmovsxbd
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; AVX: vpmovsxdq
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; AVX: vpmovsxdq
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; AVX: ret
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define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) {
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%X = load <4 x i8>* %ptr
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%Y = sext <4 x i8> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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; AVX: sext_4i16_to_4i64
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; AVX: vpmovsxwd
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; AVX: vpmovsxdq
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; AVX: vpmovsxdq
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; AVX: ret
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define <4 x i64> @load_sext_4i16_to_4i64(<4 x i16> *%ptr) {
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%X = load <4 x i16>* %ptr
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%Y = sext <4 x i16> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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