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Mips16RegisterInfo/MipsSERegisterInfo. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162413 91177308-0d34-0410-b5e6-96231b3b80d8
199 lines
5.9 KiB
C++
199 lines
5.9 KiB
C++
//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-reg-info"
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#include "MipsRegisterInfo.h"
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#include "Mips.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsInstrInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsMachineFunction.h"
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#include "llvm/Constants.h"
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#include "llvm/DebugInfo.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#define GET_REGINFO_TARGET_DESC
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#include "MipsGenRegisterInfo.inc"
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using namespace llvm;
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MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
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: MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
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unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
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//===----------------------------------------------------------------------===//
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// Callee Saved Registers methods
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//===----------------------------------------------------------------------===//
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/// Mips Callee Saved Registers
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const uint16_t* MipsRegisterInfo::
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getCalleeSavedRegs(const MachineFunction *MF) const {
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if (Subtarget.isSingleFloat())
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return CSR_SingleFloatOnly_SaveList;
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else if (!Subtarget.hasMips64())
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return CSR_O32_SaveList;
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else if (Subtarget.isABI_N32())
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return CSR_N32_SaveList;
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assert(Subtarget.isABI_N64());
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return CSR_N64_SaveList;
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}
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const uint32_t*
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MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
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if (Subtarget.isSingleFloat())
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return CSR_SingleFloatOnly_RegMask;
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else if (!Subtarget.hasMips64())
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return CSR_O32_RegMask;
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else if (Subtarget.isABI_N32())
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return CSR_N32_RegMask;
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assert(Subtarget.isABI_N64());
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return CSR_N64_RegMask;
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}
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BitVector MipsRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const {
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static const uint16_t ReservedCPURegs[] = {
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Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, Mips::SP
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};
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static const uint16_t ReservedCPU64Regs[] = {
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Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
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};
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BitVector Reserved(getNumRegs());
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typedef TargetRegisterClass::const_iterator RegIter;
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for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
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Reserved.set(ReservedCPURegs[I]);
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if (Subtarget.hasMips64()) {
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for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
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Reserved.set(ReservedCPU64Regs[I]);
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// Reserve all registers in AFGR64.
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for (RegIter Reg = Mips::AFGR64RegClass.begin(),
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EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
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Reserved.set(*Reg);
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} else {
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// Reserve all registers in CPU64Regs & FGR64.
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for (RegIter Reg = Mips::CPU64RegsRegClass.begin(),
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EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg)
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Reserved.set(*Reg);
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for (RegIter Reg = Mips::FGR64RegClass.begin(),
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EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
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Reserved.set(*Reg);
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}
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// Reserve FP if this function should have a dedicated frame pointer register.
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if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
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Reserved.set(Mips::FP);
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Reserved.set(Mips::FP_64);
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}
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// Reserve hardware registers.
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Reserved.set(Mips::HWR29);
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Reserved.set(Mips::HWR29_64);
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// Reserve RA if in mips16 mode.
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if (Subtarget.inMips16Mode()) {
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Reserved.set(Mips::RA);
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Reserved.set(Mips::RA_64);
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}
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// Reserve GP if small section is used.
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if (Subtarget.useSmallSection()) {
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Reserved.set(Mips::GP);
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Reserved.set(Mips::GP_64);
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}
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return Reserved;
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}
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bool
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MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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bool
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MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
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return true;
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}
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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void MipsRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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RegScavenger *RS) const {
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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unsigned i = 0;
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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}
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DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
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errs() << "<--------->\n" << MI);
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int FrameIndex = MI.getOperand(i).getIndex();
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uint64_t stackSize = MF.getFrameInfo()->getStackSize();
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int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
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<< "spOffset : " << spOffset << "\n"
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<< "stackSize : " << stackSize << "\n");
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eliminateFI(MI, i, FrameIndex, stackSize, spOffset);
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}
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unsigned MipsRegisterInfo::
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getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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bool IsN64 = Subtarget.isABI_N64();
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return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
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(IsN64 ? Mips::SP_64 : Mips::SP);
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}
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unsigned MipsRegisterInfo::
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getEHExceptionRegister() const {
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llvm_unreachable("What is the exception register");
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}
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unsigned MipsRegisterInfo::
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getEHHandlerRegister() const {
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llvm_unreachable("What is the exception handler register");
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}
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