Kalle Raiskila 31cbac1cfe Allow vector shifts (shl,lshr,ashr) on SPU. ... There was a previous implementation with patterns that would have matched e.g. shl <v4i32> <i32>, but this is not valid LLVM IR so they never were selected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8		2011-03-04 13:19:18 +00:00
..
Analysis
Archive
Assembler
Bindings/Ocaml
Bitcode
BugPoint
CodeGen	Allow vector shifts (shl,lshr,ashr) on SPU.	2011-03-04 13:19:18 +00:00
DebugInfo	Remove obsolete tests.	2011-02-24 19:09:52 +00:00
ExecutionEngine
Feature
FrontendAda
FrontendC	Test case for r126672. Radar 9055247.	2011-03-02 23:24:44 +00:00
FrontendC++
FrontendFortran
FrontendObjC	Check the ASM, not LLVM IR.	2011-03-03 02:02:12 +00:00
FrontendObjC++
Integer
lib
Linker
LLVMC
MC	Followup to r126970: add 64-bit encoding tests for str with reg operand.	2011-03-04 04:06:47 +00:00
Object
Other
Scripts
TableGen
Transforms	Fold "icmp pred (srem X, Y), Y" like we do for urem. Handle signed comparisons	2011-03-04 10:06:52 +00:00
Unit
Verifier
CMakeLists.txt
lit.cfg	test/lit.cfg: Add PATHEXT to 'substitution', to recognize tools on Windows hosts. Thanks to Danil Malyshev!	2011-02-24 12:34:34 +00:00
lit.site.cfg.in
Makefile
Makefile.tests
site.exp.in
TestRunner.sh