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https://github.com/c64scene-ar/llvm-6502.git
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5d787bb93e
types. These tests mimic the integer test cases in the normal InstCombine test suite but use "strange" integer bit widths. Most tests written by Zhou Sheng, a few by me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35284 91177308-0d34-0410-b5e6-96231b3b80d8
84 lines
2.0 KiB
LLVM
84 lines
2.0 KiB
LLVM
; This test makes sure that and instructions are properly eliminated.
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; This test is for Integer BitWidth > 64 && BitWidth <= 1024.
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; RUN: llvm-as < %s | opt -instcombine -disable-output &&
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; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep 'and '
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implementation
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define i999 @test0(i999 %A) {
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%B = and i999 %A, 0 ; zero result
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ret i999 %B
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}
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define i477 @test1(i477 %A, i477 %B) {
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;; (~A & ~B) == (~(A | B)) - De Morgan's Law
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%NotA = xor i477 %A, -1
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%NotB = xor i477 %B, -1
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%C1 = and i477 %NotA, %NotB
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ret i477 %C1
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}
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define i129 @tst(i129 %A, i129 %B) {
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;; (~A & ~B) == (~(A | B)) - De Morgan's Law
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%NotA = xor i129 %A, -1
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%NotB = xor i129 %B, -1
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%C1 = and i129 %NotA, %NotB
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ret i129 %C1
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}
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define i65 @test(i65 %A, i65 %B) {
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;; (~A & ~B) == (~(A | B)) - De Morgan's Law
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%NotA = xor i65 %A, -1
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%NotB = xor i65 -1, %B
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%C1 = and i65 %NotA, %NotB
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ret i65 %C1
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}
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define i66 @tes(i66 %A, i66 %B) {
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;; (~A & ~B) == (~(A | B)) - De Morgan's Law
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%NotA = xor i66 %A, -1
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%NotB = xor i66 %B, -1
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%C1 = and i66 %NotA, %NotB
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ret i66 %C1
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}
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define i1005 @test2(i1005 %x) {
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%tmp.2 = and i1005 %x, -1 ; noop
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ret i1005 %tmp.2
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}
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define i123 @test3(i123 %x) {
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%tmp.0 = and i123 %x, 127
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%tmp.2 = and i123 %tmp.0, 128
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ret i123 %tmp.2
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}
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define i1 @test4(i737 %x) {
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%A = and i737 %x, -2147483648
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%B = icmp ne i737 %A, 0
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ret i1 %B
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}
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define i117 @test5(i117 %A, i117* %P) {
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%B = or i117 %A, 3
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%C = xor i117 %B, 12
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store i117 %C, i117* %P
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%r = and i117 %C, 3
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ret i117 %r
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}
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define i117 @test6(i117 %A, i117 %B) {
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;; ~(~X & Y) --> (X | ~Y)
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%t0 = xor i117 %A, -1
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%t1 = and i117 %t0, %B
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%r = xor i117 %t1, -1
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ret i117 %r
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}
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define i1024 @test7(i1024 %A) {
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%X = ashr i1024 %A, 1016 ;; sign extend
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%C1 = and i1024 %X, 255
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ret i1024 %C1
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}
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