mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 21:29:28 +00:00
This is a follow up to r227113. It is now required to use the amdgcn target for SI and newer GPUs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227316 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
2.5 KiB
C++
80 lines
2.5 KiB
C++
//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
/// \brief The AMDGPU TargetMachine interface definition for hw codgen targets.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETMACHINE_H
|
|
#define LLVM_LIB_TARGET_R600_AMDGPUTARGETMACHINE_H
|
|
|
|
#include "AMDGPUFrameLowering.h"
|
|
#include "AMDGPUInstrInfo.h"
|
|
#include "AMDGPUIntrinsicInfo.h"
|
|
#include "AMDGPUSubtarget.h"
|
|
#include "R600ISelLowering.h"
|
|
#include "llvm/IR/DataLayout.h"
|
|
|
|
namespace llvm {
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// AMDGPU Target Machine (R600+)
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class AMDGPUTargetMachine : public LLVMTargetMachine {
|
|
private:
|
|
const DataLayout DL;
|
|
|
|
protected:
|
|
TargetLoweringObjectFile *TLOF;
|
|
AMDGPUSubtarget Subtarget;
|
|
AMDGPUIntrinsicInfo IntrinsicInfo;
|
|
|
|
public:
|
|
AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,
|
|
StringRef CPU, TargetOptions Options, Reloc::Model RM,
|
|
CodeModel::Model CM, CodeGenOpt::Level OL);
|
|
~AMDGPUTargetMachine();
|
|
// FIXME: This is currently broken, the DataLayout needs to move to
|
|
// the target machine.
|
|
const DataLayout *getDataLayout() const override {
|
|
return &DL;
|
|
}
|
|
const AMDGPUSubtarget *getSubtargetImpl() const override {
|
|
return &Subtarget;
|
|
}
|
|
const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
|
|
return &IntrinsicInfo;
|
|
}
|
|
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
|
|
|
|
/// \brief Register R600 analysis passes with a pass manager.
|
|
void addAnalysisPasses(PassManagerBase &PM) override;
|
|
TargetLoweringObjectFile *getObjFileLowering() const override {
|
|
return TLOF;
|
|
}
|
|
};
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// GCN Target Machine (SI+)
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class GCNTargetMachine : public AMDGPUTargetMachine {
|
|
|
|
public:
|
|
GCNTargetMachine(const Target &T, StringRef TT, StringRef FS,
|
|
StringRef CPU, TargetOptions Options, Reloc::Model RM,
|
|
CodeModel::Model CM, CodeGenOpt::Level OL);
|
|
};
|
|
|
|
} // End namespace llvm
|
|
|
|
#endif
|