mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
24517d023f
The current memory-instruction optimization logic in CGP, which sinks parts of
the address computation that can be adsorbed by the addressing mode, does this
by explicitly converting the relevant part of the address computation into
IR-level integer operations (making use of ptrtoint and inttoptr). For most
targets this is currently not a problem, but for targets wishing to make use of
IR-level aliasing analysis during CodeGen, the use of ptrtoint/inttoptr is a
problem for two reasons:
1. BasicAA becomes less powerful in the face of the ptrtoint/inttoptr
2. In cases where type-punning was used, and BasicAA was used
to override TBAA, BasicAA may no longer do so. (this had forced us to disable
all use of TBAA in CodeGen; something which we can now enable again)
This (use of GEPs instead of ptrtoint/inttoptr) is not currently enabled by
default (except for those targets that use AA during CodeGen), and so aside
from some PowerPC subtargets and SystemZ, there should be no change in
behavior. We may be able to switch completely away from the ptrtoint/inttoptr
sinking on all targets, but further testing is required.
I've doubled-up on a number of existing tests that are sensitive to the
address sinking behavior (including some store-merging tests that are
sensitive to the order of the resulting ADD operations at the SDAG level).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206092 91177308-0d34-0410-b5e6-96231b3b80d8
371 lines
15 KiB
LLVM
371 lines
15 KiB
LLVM
; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=A9
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; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a9 -addr-sink-using-gep=1 %s -o - | FileCheck %s -check-prefix=A9
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; @simple is the most basic chain of address induction variables. Chaining
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; saves at least one register and avoids complex addressing and setup
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; code.
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;
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; A9: @simple
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; no expensive address computation in the preheader
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; A9: lsl
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; A9-NOT: lsl
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; A9: %loop
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; no complex address modes
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; A9-NOT: lsl
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define i32 @simple(i32* %a, i32* %b, i32 %x) nounwind {
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entry:
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br label %loop
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loop:
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%iv = phi i32* [ %a, %entry ], [ %iv4, %loop ]
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%s = phi i32 [ 0, %entry ], [ %s4, %loop ]
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%v = load i32* %iv
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%iv1 = getelementptr inbounds i32* %iv, i32 %x
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%v1 = load i32* %iv1
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%iv2 = getelementptr inbounds i32* %iv1, i32 %x
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%v2 = load i32* %iv2
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%iv3 = getelementptr inbounds i32* %iv2, i32 %x
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%v3 = load i32* %iv3
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%s1 = add i32 %s, %v
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%s2 = add i32 %s1, %v1
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%s3 = add i32 %s2, %v2
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%s4 = add i32 %s3, %v3
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%iv4 = getelementptr inbounds i32* %iv3, i32 %x
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%cmp = icmp eq i32* %iv4, %b
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br i1 %cmp, label %exit, label %loop
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exit:
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ret i32 %s4
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}
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; @user is not currently chained because the IV is live across memory ops.
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;
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; A9: @user
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; stride multiples computed in the preheader
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; A9: lsl
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; A9: lsl
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; A9: %loop
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; complex address modes
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; A9: lsl
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; A9: lsl
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define i32 @user(i32* %a, i32* %b, i32 %x) nounwind {
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entry:
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br label %loop
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loop:
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%iv = phi i32* [ %a, %entry ], [ %iv4, %loop ]
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%s = phi i32 [ 0, %entry ], [ %s4, %loop ]
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%v = load i32* %iv
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%iv1 = getelementptr inbounds i32* %iv, i32 %x
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%v1 = load i32* %iv1
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%iv2 = getelementptr inbounds i32* %iv1, i32 %x
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%v2 = load i32* %iv2
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%iv3 = getelementptr inbounds i32* %iv2, i32 %x
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%v3 = load i32* %iv3
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%s1 = add i32 %s, %v
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%s2 = add i32 %s1, %v1
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%s3 = add i32 %s2, %v2
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%s4 = add i32 %s3, %v3
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%iv4 = getelementptr inbounds i32* %iv3, i32 %x
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store i32 %s4, i32* %iv
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%cmp = icmp eq i32* %iv4, %b
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br i1 %cmp, label %exit, label %loop
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exit:
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ret i32 %s4
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}
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; @extrastride is a slightly more interesting case of a single
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; complete chain with multiple strides. The test case IR is what LSR
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; used to do, and exactly what we don't want to do. LSR's new IV
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; chaining feature should now undo the damage.
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;
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; A9: extrastride:
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; no spills
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; A9-NOT: str
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; only one stride multiple in the preheader
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; A9: lsl
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; A9-NOT: {{str r|lsl}}
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; A9: %for.body{{$}}
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; no complex address modes or reloads
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; A9-NOT: {{ldr .*[sp]|lsl}}
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define void @extrastride(i8* nocapture %main, i32 %main_stride, i32* nocapture %res, i32 %x, i32 %y, i32 %z) nounwind {
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entry:
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%cmp8 = icmp eq i32 %z, 0
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br i1 %cmp8, label %for.end, label %for.body.lr.ph
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for.body.lr.ph: ; preds = %entry
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%add.ptr.sum = shl i32 %main_stride, 1 ; s*2
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%add.ptr1.sum = add i32 %add.ptr.sum, %main_stride ; s*3
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%add.ptr2.sum = add i32 %x, %main_stride ; s + x
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%add.ptr4.sum = shl i32 %main_stride, 2 ; s*4
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%add.ptr3.sum = add i32 %add.ptr2.sum, %add.ptr4.sum ; total IV stride = s*5+x
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br label %for.body
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for.body: ; preds = %for.body.lr.ph, %for.body
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%main.addr.011 = phi i8* [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ]
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%i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
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%res.addr.09 = phi i32* [ %res, %for.body.lr.ph ], [ %add.ptr7, %for.body ]
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%0 = bitcast i8* %main.addr.011 to i32*
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%1 = load i32* %0, align 4
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%add.ptr = getelementptr inbounds i8* %main.addr.011, i32 %main_stride
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%2 = bitcast i8* %add.ptr to i32*
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%3 = load i32* %2, align 4
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%add.ptr1 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr.sum
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%4 = bitcast i8* %add.ptr1 to i32*
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%5 = load i32* %4, align 4
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%add.ptr2 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr1.sum
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%6 = bitcast i8* %add.ptr2 to i32*
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%7 = load i32* %6, align 4
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%add.ptr3 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr4.sum
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%8 = bitcast i8* %add.ptr3 to i32*
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%9 = load i32* %8, align 4
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%add = add i32 %3, %1
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%add4 = add i32 %add, %5
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%add5 = add i32 %add4, %7
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%add6 = add i32 %add5, %9
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store i32 %add6, i32* %res.addr.09, align 4
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%add.ptr6 = getelementptr inbounds i8* %main.addr.011, i32 %add.ptr3.sum
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%add.ptr7 = getelementptr inbounds i32* %res.addr.09, i32 %y
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%inc = add i32 %i.010, 1
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%cmp = icmp eq i32 %inc, %z
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br i1 %cmp, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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; @foldedidx is an unrolled variant of this loop:
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; for (unsigned long i = 0; i < len; i += s) {
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; c[i] = a[i] + b[i];
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; }
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; where 's' can be folded into the addressing mode.
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; Consequently, we should *not* form any chains.
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;
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; A9: foldedidx:
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; A9: ldrb{{(.w)?}} {{r[0-9]|lr}}, [{{r[0-9]|lr}}, #3]
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define void @foldedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c) nounwind ssp {
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.07 = phi i32 [ 0, %entry ], [ %inc.3, %for.body ]
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%arrayidx = getelementptr inbounds i8* %a, i32 %i.07
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%0 = load i8* %arrayidx, align 1
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%conv5 = zext i8 %0 to i32
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%arrayidx1 = getelementptr inbounds i8* %b, i32 %i.07
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%1 = load i8* %arrayidx1, align 1
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%conv26 = zext i8 %1 to i32
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%add = add nsw i32 %conv26, %conv5
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%conv3 = trunc i32 %add to i8
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%arrayidx4 = getelementptr inbounds i8* %c, i32 %i.07
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store i8 %conv3, i8* %arrayidx4, align 1
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%inc1 = or i32 %i.07, 1
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%arrayidx.1 = getelementptr inbounds i8* %a, i32 %inc1
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%2 = load i8* %arrayidx.1, align 1
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%conv5.1 = zext i8 %2 to i32
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%arrayidx1.1 = getelementptr inbounds i8* %b, i32 %inc1
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%3 = load i8* %arrayidx1.1, align 1
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%conv26.1 = zext i8 %3 to i32
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%add.1 = add nsw i32 %conv26.1, %conv5.1
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%conv3.1 = trunc i32 %add.1 to i8
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%arrayidx4.1 = getelementptr inbounds i8* %c, i32 %inc1
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store i8 %conv3.1, i8* %arrayidx4.1, align 1
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%inc.12 = or i32 %i.07, 2
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%arrayidx.2 = getelementptr inbounds i8* %a, i32 %inc.12
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%4 = load i8* %arrayidx.2, align 1
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%conv5.2 = zext i8 %4 to i32
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%arrayidx1.2 = getelementptr inbounds i8* %b, i32 %inc.12
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%5 = load i8* %arrayidx1.2, align 1
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%conv26.2 = zext i8 %5 to i32
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%add.2 = add nsw i32 %conv26.2, %conv5.2
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%conv3.2 = trunc i32 %add.2 to i8
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%arrayidx4.2 = getelementptr inbounds i8* %c, i32 %inc.12
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store i8 %conv3.2, i8* %arrayidx4.2, align 1
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%inc.23 = or i32 %i.07, 3
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%arrayidx.3 = getelementptr inbounds i8* %a, i32 %inc.23
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%6 = load i8* %arrayidx.3, align 1
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%conv5.3 = zext i8 %6 to i32
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%arrayidx1.3 = getelementptr inbounds i8* %b, i32 %inc.23
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%7 = load i8* %arrayidx1.3, align 1
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%conv26.3 = zext i8 %7 to i32
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%add.3 = add nsw i32 %conv26.3, %conv5.3
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%conv3.3 = trunc i32 %add.3 to i8
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%arrayidx4.3 = getelementptr inbounds i8* %c, i32 %inc.23
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store i8 %conv3.3, i8* %arrayidx4.3, align 1
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%inc.3 = add nsw i32 %i.07, 4
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%exitcond.3 = icmp eq i32 %inc.3, 400
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br i1 %exitcond.3, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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; @testNeon is an important example of the nead for ivchains.
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;
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; Currently we have three extra add.w's that keep the store address
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; live past the next increment because ISEL is unfortunately undoing
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; the store chain. ISEL also fails to convert the stores to
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; post-increment addressing. However, the loads should use
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; post-increment addressing, no add's or add.w's beyond the three
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; mentioned. Most importantly, there should be no spills or reloads!
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;
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; A9: testNeon:
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; A9: %.lr.ph
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; A9-NOT: lsl.w
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; A9-NOT: {{ldr|str|adds|add r}}
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; A9: add.w r
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; A9-NOT: {{ldr|str|adds|add r}}
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; A9: add.w r
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; A9-NOT: {{ldr|str|adds|add r}}
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; A9: add.w r
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; A9-NOT: {{ldr|str|adds|add r}}
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; A9-NOT: add.w r
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; A9: bne
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define hidden void @testNeon(i8* %ref_data, i32 %ref_stride, i32 %limit, <16 x i8>* nocapture %data) nounwind optsize {
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%1 = icmp sgt i32 %limit, 0
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br i1 %1, label %.lr.ph, label %45
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.lr.ph: ; preds = %0
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%2 = shl nsw i32 %ref_stride, 1
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%3 = mul nsw i32 %ref_stride, 3
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%4 = shl nsw i32 %ref_stride, 2
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%5 = mul nsw i32 %ref_stride, 5
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%6 = mul nsw i32 %ref_stride, 6
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%7 = mul nsw i32 %ref_stride, 7
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%8 = shl nsw i32 %ref_stride, 3
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%9 = sub i32 0, %8
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%10 = mul i32 %limit, -64
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br label %11
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; <label>:11 ; preds = %11, %.lr.ph
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%.05 = phi i8* [ %ref_data, %.lr.ph ], [ %42, %11 ]
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%counter.04 = phi i32 [ 0, %.lr.ph ], [ %44, %11 ]
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%result.03 = phi <16 x i8> [ zeroinitializer, %.lr.ph ], [ %41, %11 ]
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%.012 = phi <16 x i8>* [ %data, %.lr.ph ], [ %43, %11 ]
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%12 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %.05, i32 1) nounwind
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%13 = getelementptr inbounds i8* %.05, i32 %ref_stride
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%14 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %13, i32 1) nounwind
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%15 = shufflevector <1 x i64> %12, <1 x i64> %14, <2 x i32> <i32 0, i32 1>
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%16 = bitcast <2 x i64> %15 to <16 x i8>
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%17 = getelementptr inbounds <16 x i8>* %.012, i32 1
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store <16 x i8> %16, <16 x i8>* %.012, align 4
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%18 = getelementptr inbounds i8* %.05, i32 %2
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%19 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %18, i32 1) nounwind
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%20 = getelementptr inbounds i8* %.05, i32 %3
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%21 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %20, i32 1) nounwind
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%22 = shufflevector <1 x i64> %19, <1 x i64> %21, <2 x i32> <i32 0, i32 1>
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%23 = bitcast <2 x i64> %22 to <16 x i8>
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%24 = getelementptr inbounds <16 x i8>* %.012, i32 2
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store <16 x i8> %23, <16 x i8>* %17, align 4
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%25 = getelementptr inbounds i8* %.05, i32 %4
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%26 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %25, i32 1) nounwind
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%27 = getelementptr inbounds i8* %.05, i32 %5
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%28 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %27, i32 1) nounwind
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%29 = shufflevector <1 x i64> %26, <1 x i64> %28, <2 x i32> <i32 0, i32 1>
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%30 = bitcast <2 x i64> %29 to <16 x i8>
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%31 = getelementptr inbounds <16 x i8>* %.012, i32 3
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store <16 x i8> %30, <16 x i8>* %24, align 4
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%32 = getelementptr inbounds i8* %.05, i32 %6
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%33 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %32, i32 1) nounwind
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%34 = getelementptr inbounds i8* %.05, i32 %7
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%35 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %34, i32 1) nounwind
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%36 = shufflevector <1 x i64> %33, <1 x i64> %35, <2 x i32> <i32 0, i32 1>
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%37 = bitcast <2 x i64> %36 to <16 x i8>
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store <16 x i8> %37, <16 x i8>* %31, align 4
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%38 = add <16 x i8> %16, %23
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%39 = add <16 x i8> %38, %30
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%40 = add <16 x i8> %39, %37
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%41 = add <16 x i8> %result.03, %40
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%42 = getelementptr i8* %.05, i32 %9
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%43 = getelementptr inbounds <16 x i8>* %.012, i32 -64
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%44 = add nsw i32 %counter.04, 1
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%exitcond = icmp eq i32 %44, %limit
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br i1 %exitcond, label %._crit_edge, label %11
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._crit_edge: ; preds = %11
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%scevgep = getelementptr <16 x i8>* %data, i32 %10
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br label %45
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; <label>:45 ; preds = %._crit_edge, %0
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%result.0.lcssa = phi <16 x i8> [ %41, %._crit_edge ], [ zeroinitializer, %0 ]
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%.01.lcssa = phi <16 x i8>* [ %scevgep, %._crit_edge ], [ %data, %0 ]
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store <16 x i8> %result.0.lcssa, <16 x i8>* %.01.lcssa, align 4
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ret void
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}
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declare <1 x i64> @llvm.arm.neon.vld1.v1i64(i8*, i32) nounwind readonly
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; Handle chains in which the same offset is used for both loads and
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; stores to the same array.
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; rdar://11410078.
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;
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; A9: @testReuse
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; A9: %for.body
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE:[r[0-9]+]]], [[INC:r[0-9]]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], {{r[0-9]}}
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]]
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; A9: bne
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define void @testReuse(i8* %src, i32 %stride) nounwind ssp {
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entry:
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%mul = shl nsw i32 %stride, 2
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%idx.neg = sub i32 0, %mul
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%mul1 = mul nsw i32 %stride, 3
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%idx.neg2 = sub i32 0, %mul1
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%mul5 = shl nsw i32 %stride, 1
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%idx.neg6 = sub i32 0, %mul5
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%idx.neg10 = sub i32 0, %stride
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.0110 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%src.addr = phi i8* [ %src, %entry ], [ %add.ptr45, %for.body ]
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%add.ptr = getelementptr inbounds i8* %src.addr, i32 %idx.neg
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%vld1 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr, i32 1)
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%add.ptr3 = getelementptr inbounds i8* %src.addr, i32 %idx.neg2
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%vld2 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr3, i32 1)
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%add.ptr7 = getelementptr inbounds i8* %src.addr, i32 %idx.neg6
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%vld3 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr7, i32 1)
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%add.ptr11 = getelementptr inbounds i8* %src.addr, i32 %idx.neg10
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%vld4 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr11, i32 1)
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%vld5 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %src.addr, i32 1)
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%add.ptr17 = getelementptr inbounds i8* %src.addr, i32 %stride
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%vld6 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr17, i32 1)
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%add.ptr20 = getelementptr inbounds i8* %src.addr, i32 %mul5
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%vld7 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr20, i32 1)
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%add.ptr23 = getelementptr inbounds i8* %src.addr, i32 %mul1
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%vld8 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr23, i32 1)
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%vadd1 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld1, <8 x i8> %vld2) nounwind
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%vadd2 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld2, <8 x i8> %vld3) nounwind
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%vadd3 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld3, <8 x i8> %vld4) nounwind
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%vadd4 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld4, <8 x i8> %vld5) nounwind
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%vadd5 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld5, <8 x i8> %vld6) nounwind
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%vadd6 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld6, <8 x i8> %vld7) nounwind
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr3, <8 x i8> %vadd1, i32 1)
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr7, <8 x i8> %vadd2, i32 1)
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr11, <8 x i8> %vadd3, i32 1)
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %src.addr, <8 x i8> %vadd4, i32 1)
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr17, <8 x i8> %vadd5, i32 1)
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr20, <8 x i8> %vadd6, i32 1)
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%inc = add nsw i32 %i.0110, 1
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%add.ptr45 = getelementptr inbounds i8* %src.addr, i32 8
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%exitcond = icmp eq i32 %inc, 4
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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declare <8 x i8> @llvm.arm.neon.vld1.v8i8(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind
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declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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