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https://github.com/c64scene-ar/llvm-6502.git
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Newer POWER cores, and the A2, support the cmpb instruction. This instruction compares its operands, treating each of the 8 bytes in the GPRs separately, returning a 'mask' result of 0 (for false) or -1 (for true) in each byte. Code generation support is added, in the form of a PPCISelDAGToDAG DAG-preprocessing routine, that recognizes patterns close to what the instruction computes (either exactly, or related by a constant masking operation), and generates the cmpb instruction (along with any necessary constant masking operation). This can be expanded if use cases arise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225106 91177308-0d34-0410-b5e6-96231b3b80d8
205 lines
5.7 KiB
LLVM
205 lines
5.7 KiB
LLVM
; RUN: llc -mcpu pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind readnone
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define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 {
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entry:
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%0 = xor i16 %y, %x
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%1 = and i16 %0, 255
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%cmp = icmp eq i16 %1, 0
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%cmp20 = icmp ult i16 %0, 256
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%conv25 = select i1 %cmp, i32 255, i32 0
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%conv27 = select i1 %cmp20, i32 65280, i32 0
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%or = or i32 %conv25, %conv27
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%conv29 = trunc i32 %or to i16
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ret i16 %conv29
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; CHECK-LABEL: @test16
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; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
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; CHECK: rldicl 3, [[REG1]], 0, 48
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; CHECK: blr
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}
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define zeroext i16 @test16p1(i16 zeroext %x, i16 zeroext %y) #0 {
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entry:
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%0 = xor i16 %y, %x
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%1 = and i16 %0, 255
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%cmp = icmp eq i16 %1, 0
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%cmp20 = icmp ult i16 %0, 256
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%conv28 = select i1 %cmp, i32 5, i32 0
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%conv30 = select i1 %cmp20, i32 65280, i32 0
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%or = or i32 %conv28, %conv30
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%conv32 = trunc i32 %or to i16
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ret i16 %conv32
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; CHECK-LABEL: @test16p1
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; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
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; CHECK: andi. 3, [[REG1]], 65285
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define zeroext i16 @test16p2(i16 zeroext %x, i16 zeroext %y) #0 {
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entry:
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%0 = xor i16 %y, %x
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%1 = and i16 %0, 255
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%cmp = icmp eq i16 %1, 0
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%cmp20 = icmp ult i16 %0, 256
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%conv28 = select i1 %cmp, i32 255, i32 0
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%conv30 = select i1 %cmp20, i32 1280, i32 0
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%or = or i32 %conv28, %conv30
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%conv32 = trunc i32 %or to i16
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ret i16 %conv32
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; CHECK-LABEL: @test16p2
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; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
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; CHECK: andi. 3, [[REG1]], 1535
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define zeroext i16 @test16p3(i16 zeroext %x, i16 zeroext %y) #0 {
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entry:
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%0 = xor i16 %y, %x
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%1 = and i16 %0, 255
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%cmp = icmp eq i16 %1, 0
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%cmp20 = icmp ult i16 %0, 256
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%conv27 = select i1 %cmp, i32 255, i32 0
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%conv29 = select i1 %cmp20, i32 1024, i32 1280
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%or = or i32 %conv27, %conv29
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%conv31 = trunc i32 %or to i16
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ret i16 %conv31
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; CHECK-LABEL: @test16p3
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; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
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; CHECK: rldicl [[REG2:[0-9]+]], [[REG1]], 0, 55
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; CHECK: xori 3, [[REG2]], 1280
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; CHECK: blr
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}
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define zeroext i32 @test32(i32 zeroext %x, i32 zeroext %y) #0 {
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entry:
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%0 = xor i32 %y, %x
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%1 = and i32 %0, 255
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%cmp = icmp eq i32 %1, 0
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%2 = and i32 %0, 65280
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%cmp28 = icmp eq i32 %2, 0
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%3 = and i32 %0, 16711680
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%cmp34 = icmp eq i32 %3, 0
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%cmp40 = icmp ult i32 %0, 16777216
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%conv44 = select i1 %cmp, i32 255, i32 0
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%conv45 = select i1 %cmp28, i32 65280, i32 0
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%conv47 = select i1 %cmp34, i32 16711680, i32 0
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%conv50 = select i1 %cmp40, i32 -16777216, i32 0
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%or = or i32 %conv45, %conv50
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%or49 = or i32 %or, %conv44
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%or52 = or i32 %or49, %conv47
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ret i32 %or52
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; CHECK-LABEL: @test32
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; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
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; CHECK: rldicl 3, [[REG1]], 0, 32
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; CHECK: blr
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}
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define zeroext i32 @test32p1(i32 zeroext %x, i32 zeroext %y) #0 {
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entry:
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%0 = xor i32 %y, %x
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%1 = and i32 %0, 255
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%cmp = icmp eq i32 %1, 0
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%2 = and i32 %0, 65280
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%cmp28 = icmp eq i32 %2, 0
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%3 = and i32 %0, 16711680
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%cmp34 = icmp eq i32 %3, 0
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%cmp40 = icmp ult i32 %0, 16777216
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%conv47 = select i1 %cmp, i32 255, i32 0
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%conv48 = select i1 %cmp28, i32 65280, i32 0
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%conv50 = select i1 %cmp34, i32 458752, i32 0
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%conv53 = select i1 %cmp40, i32 -16777216, i32 0
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%or = or i32 %conv48, %conv53
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%or52 = or i32 %or, %conv47
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%or55 = or i32 %or52, %conv50
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ret i32 %or55
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; CHECK-LABEL: @test32p1
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; CHECK: li [[REG1:[0-9]+]], 0
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; CHECK: cmpb [[REG4:[0-9]+]], 4, 3
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; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 65287
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; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535
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; CHECK: and 3, [[REG4]], [[REG3]]
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; CHECK: blr
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}
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define zeroext i32 @test32p2(i32 zeroext %x, i32 zeroext %y) #0 {
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entry:
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%0 = xor i32 %y, %x
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%1 = and i32 %0, 255
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%cmp = icmp eq i32 %1, 0
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%2 = and i32 %0, 65280
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%cmp22 = icmp eq i32 %2, 0
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%cmp28 = icmp ult i32 %0, 16777216
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%conv32 = select i1 %cmp, i32 255, i32 0
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%conv33 = select i1 %cmp22, i32 65280, i32 0
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%conv35 = select i1 %cmp28, i32 -16777216, i32 0
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%or = or i32 %conv33, %conv35
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%or37 = or i32 %or, %conv32
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ret i32 %or37
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; CHECK-LABEL: @test32p2
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; CHECK: li [[REG1:[0-9]+]], 0
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; CHECK: cmpb [[REG4:[0-9]+]], 4, 3
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; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 65280
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; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535
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; CHECK: and 3, [[REG4]], [[REG3]]
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; CHECK: blr
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}
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define i64 @test64(i64 %x, i64 %y) #0 {
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entry:
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%shr19 = lshr i64 %x, 56
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%conv21 = trunc i64 %shr19 to i32
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%shr43 = lshr i64 %y, 56
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%conv45 = trunc i64 %shr43 to i32
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%0 = xor i64 %y, %x
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%1 = and i64 %0, 255
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%cmp = icmp eq i64 %1, 0
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%2 = and i64 %0, 65280
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%cmp52 = icmp eq i64 %2, 0
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%3 = and i64 %0, 16711680
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%cmp58 = icmp eq i64 %3, 0
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%4 = and i64 %0, 4278190080
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%cmp64 = icmp eq i64 %4, 0
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%5 = and i64 %0, 1095216660480
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%cmp70 = icmp eq i64 %5, 0
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%6 = and i64 %0, 280375465082880
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%cmp76 = icmp eq i64 %6, 0
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%7 = and i64 %0, 71776119061217280
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%cmp82 = icmp eq i64 %7, 0
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%cmp88 = icmp eq i32 %conv21, %conv45
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%conv92 = select i1 %cmp, i64 255, i64 0
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%conv93 = select i1 %cmp52, i64 65280, i64 0
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%or = or i64 %conv92, %conv93
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%conv95 = select i1 %cmp58, i64 16711680, i64 0
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%or97 = or i64 %or, %conv95
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%conv98 = select i1 %cmp64, i64 4278190080, i64 0
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%or100 = or i64 %or97, %conv98
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%conv101 = select i1 %cmp70, i64 1095216660480, i64 0
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%or103 = or i64 %or100, %conv101
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%conv104 = select i1 %cmp76, i64 280375465082880, i64 0
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%or106 = or i64 %or103, %conv104
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%conv107 = select i1 %cmp82, i64 71776119061217280, i64 0
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%or109 = or i64 %or106, %conv107
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%conv110 = select i1 %cmp88, i64 -72057594037927936, i64 0
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%or112 = or i64 %or109, %conv110
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ret i64 %or112
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; CHECK-LABEL: @test64
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; CHECK: cmpb 3, 3, 4
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; CHECK-NOT: rldicl
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; CHECK: blr
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}
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attributes #0 = { nounwind readnone }
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