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808d878a96
PR20071 identifies a problem in PowerPC's fast-isel implementation for floating-point conversion to integer. The fctiduz instruction was added in Power ISA 2.06 (i.e., Power7 and later). However, this instruction is being generated regardless of which 64-bit PowerPC target is selected. The intent is for fast-isel to punt to DAG selection when this instruction is not available. This patch implements that change. For testing purposes, the existing fast-isel-conversion.ll test adds a RUN line for -mcpu=970 and tests for the expected code generation. Additionally, the existing test fast-isel-conversion-p5.ll was found to be incorrectly expecting the unavailable instruction to be generated. I've removed these test variants since we have adequate coverage in fast-isel-conversion.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211627 91177308-0d34-0410-b5e6-96231b3b80d8
131 lines
3.0 KiB
LLVM
131 lines
3.0 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 | FileCheck %s --check-prefix=ELF64
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; Test sitofp
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define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
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entry:
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; ELF64: sitofp_double_i32
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%b.addr = alloca double, align 8
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%conv = sitofp i32 %a to double
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; ELF64: std {{[0-9]+}}, -[[OFFSET:[0-9]+]](1)
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; ELF64: lfd {{[0-9]+}}, -[[OFFSET]](1)
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; ELF64: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp {
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entry:
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; ELF64: sitofp_double_i64
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%b.addr = alloca double, align 8
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%conv = sitofp i64 %a to double
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; ELF64: std {{[0-9]+}}, -[[OFFSET:[0-9]+]](1)
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; ELF64: lfd {{[0-9]+}}, -[[OFFSET]](1)
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; ELF64: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
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entry:
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; ELF64: sitofp_double_i16
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%b.addr = alloca double, align 8
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%conv = sitofp i16 %a to double
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; ELF64: extsh
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; ELF64: std {{[0-9]+}}, -[[OFFSET:[0-9]+]](1)
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; ELF64: lfd {{[0-9]+}}, -[[OFFSET]](1)
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; ELF64: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
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entry:
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; ELF64: sitofp_double_i8
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%b.addr = alloca double, align 8
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%conv = sitofp i8 %a to double
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; ELF64: extsb
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; ELF64: std {{[0-9]+}}, -[[OFFSET:[0-9]+]](1)
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; ELF64: lfd {{[0-9]+}}, -[[OFFSET]](1)
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; ELF64: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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; Test fptosi
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define void @fptosi_float_i32(float %a) nounwind ssp {
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entry:
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; ELF64: fptosi_float_i32
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%b.addr = alloca i32, align 4
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%conv = fptosi float %a to i32
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; ELF64: fctiwz
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; ELF64: stfd
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; ELF64: lwa
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store i32 %conv, i32* %b.addr, align 4
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ret void
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}
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define void @fptosi_float_i64(float %a) nounwind ssp {
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entry:
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; ELF64: fptosi_float_i64
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%b.addr = alloca i64, align 4
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%conv = fptosi float %a to i64
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; ELF64: fctidz
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; ELF64: stfd
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; ELF64: ld
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store i64 %conv, i64* %b.addr, align 4
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ret void
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}
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define void @fptosi_double_i32(double %a) nounwind ssp {
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entry:
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; ELF64: fptosi_double_i32
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%b.addr = alloca i32, align 8
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%conv = fptosi double %a to i32
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; ELF64: fctiwz
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; ELF64: stfd
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; ELF64: lwa
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store i32 %conv, i32* %b.addr, align 8
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ret void
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}
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define void @fptosi_double_i64(double %a) nounwind ssp {
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entry:
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; ELF64: fptosi_double_i64
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%b.addr = alloca i64, align 8
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%conv = fptosi double %a to i64
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; ELF64: fctidz
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; ELF64: stfd
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; ELF64: ld
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store i64 %conv, i64* %b.addr, align 8
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ret void
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}
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; Test fptoui
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define void @fptoui_float_i32(float %a) nounwind ssp {
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entry:
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; ELF64: fptoui_float_i32
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%b.addr = alloca i32, align 4
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%conv = fptoui float %a to i32
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; ELF64: fctidz
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; ELF64: stfd
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; ELF64: lwz
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store i32 %conv, i32* %b.addr, align 4
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ret void
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}
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define void @fptoui_double_i32(double %a) nounwind ssp {
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entry:
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; ELF64: fptoui_double_i32
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%b.addr = alloca i32, align 8
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%conv = fptoui double %a to i32
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; ELF64: fctidz
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; ELF64: stfd
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; ELF64: lwz
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store i32 %conv, i32* %b.addr, align 8
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ret void
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}
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