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https://github.com/c64scene-ar/llvm-6502.git
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c9b12d06ef
The SplitIndexingFromLoad changes exposed a latent isel bug in the PowerPC64 backend. We matched an immediate offset with STWX8 even though it only supports register offset. The culprit is the complex-pattern predicate, SelectAddrIdx, which decides that if the offset is not ISD::Constant it must be a register. Many thanks to Bill Schmidt for testing this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209219 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
761 B
LLVM
23 lines
761 B
LLVM
; RUN: llc < %s | FileCheck %s
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; The SplitIndexingFromLoad tranformation exposed an isel backend bug. This
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; testcase used to generate stwx 4, 3, 64. stwx does not have an
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; immediate-offset format (note the 64) and it should not be matched.
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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%class.test = type { [64 x i8], [5 x i8] }
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; CHECK-LABEL: f:
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; CHECK-NOT: stwx {{[0-9]+}}, {{[0-9]+}}, 64
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define void @f(%class.test* %this) {
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entry:
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%Subminor.i.i = getelementptr inbounds %class.test* %this, i64 0, i32 1
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%0 = bitcast [5 x i8]* %Subminor.i.i to i40*
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%bf.load2.i.i = load i40* %0, align 4
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%bf.clear7.i.i = and i40 %bf.load2.i.i, -8589934592
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store i40 %bf.clear7.i.i, i40* %0, align 4
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ret void
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}
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